Lines Matching +full:mipi +full:- +full:to +full:- +full:edp
2 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
14 #include <linux/clk-provider.h>
28 #include "ccu-sun9i-a80.h"
35 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
37 * For now we can just model it as a multiplier clock, and force P to /1.
50 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
64 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
71 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
86 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
102 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
118 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
134 .hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
149 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
165 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
181 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
197 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
213 .hw.init = CLK_HW_INIT("pll-isp", "osc24M",
229 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
235 static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
239 static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
265 static const char * const gtbus_parents[] = { "osc24M", "pll-periph0",
266 "pll-periph1", "pll-periph1" };
270 static const char * const ahb_parents[] = { "gtbus", "pll-periph0",
271 "pll-periph1", "pll-periph1" };
308 static const char * const apb_parents[] = { "osc24M", "pll-periph0" };
370 .hw.init = CLK_HW_INIT_PARENTS("out-a",
390 .hw.init = CLK_HW_INIT_PARENTS("out-b",
397 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0" };
399 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents,
407 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_1_clk, "nand0-1", mod0_default_parents,
415 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents,
423 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_1_clk, "nand1-1", mod0_default_parents,
439 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
441 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
452 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
454 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
465 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
467 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
478 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3-sample", "mmc3",
480 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3-output", "mmc3",
491 static const char * const ss_parents[] = { "osc24M", "pll-periph",
492 "pll-periph1" };
540 static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
542 static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
544 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
547 static const char * const sdram_parents[] = { "pll-periph0", "pll-ddr" };
558 static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490,
561 static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0);
563 static const char * const mp_parents[] = { "pll-video1", "pll-gpu", "pll-de" };
572 static const char * const display_parents[] = { "pll-video0", "pll-video1" };
593 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
601 static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video1" };
603 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
620 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0);
622 static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc,
625 static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0,
628 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0);
630 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi0-mclk",
638 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi1-mclk",
646 static const char * const fd_parents[] = { "pll-periph0", "pll-isp" };
654 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0,
659 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0,
661 static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4,
664 static const char * const gpu_axi_parents[] = { "pll-periph0", "pll-gpu" };
666 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_axi_clk, "gpu-axi",
674 static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500,
677 static SUNXI_CCU_M_WITH_GATE(ac97_clk, "ac97", "pll-audio",
680 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_hsi_clk, "mipi-hsi",
687 static const char * const gpadc_parents[] = { "osc24M", "pll-audio", "osc32k" };
712 .hw.init = CLK_HW_INIT_PARENTS("cir-tx",
720 static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0",
722 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0",
724 static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0",
726 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0",
728 static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0",
730 static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0",
732 static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0",
734 static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0",
736 static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0",
738 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0",
740 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0",
742 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0",
744 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0",
746 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0",
748 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0",
752 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
754 static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1",
756 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
758 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
760 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
762 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
764 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
768 static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2",
770 static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2",
772 static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2",
774 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2",
776 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2",
778 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2",
780 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2",
782 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2",
786 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0",
788 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0",
790 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0",
792 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0",
794 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0",
796 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0",
798 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0",
800 static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0",
802 static SUNXI_CCU_GATE(bus_cir_tx_clk, "bus-cir-tx", "apb0",
806 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1",
808 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1",
810 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1",
812 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1",
814 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb1",
816 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1",
818 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1",
820 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1",
822 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1",
824 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1",
826 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1",
1205 * set P to 1, we should also decrease the multiplier so the in sun9i_a80_cpu_pll_fixup()
1209 * To keep it simple, set the multiplier to 17, the reset value. in sun9i_a80_cpu_pll_fixup()
1211 val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1, in sun9i_a80_cpu_pll_fixup()
1228 reg = devm_ioremap_resource(&pdev->dev, res); in sun9i_a80_ccu_probe()
1241 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun9i_a80_ccu_desc); in sun9i_a80_ccu_probe()
1245 { .compatible = "allwinner,sun9i-a80-ccu" },
1252 .name = "sun9i-a80-ccu",