3  * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/clk-provider.h>
23 	u8 delay;  in ccu_phase_get_phase()  local
25 	reg = readl(phase->common.base + phase->common.reg);  in ccu_phase_get_phase()
26 	delay = (reg >> phase->shift);  in ccu_phase_get_phase()
27 	delay &= (1 << phase->width) - 1;  in ccu_phase_get_phase()
29 	if (!delay)  in ccu_phase_get_phase()
32 	/* Get our parent clock, it's the one that can adjust its rate */  in ccu_phase_get_phase()
35 		return -EINVAL;  in ccu_phase_get_phase()
40 		return -EINVAL;  in ccu_phase_get_phase()
45 		return -EINVAL;  in ccu_phase_get_phase()
50 		return -EINVAL;  in ccu_phase_get_phase()
52 	/* Get our parent clock divider */  in ccu_phase_get_phase()
56 	return delay * step;  in ccu_phase_get_phase()
66 	u8 delay;  in ccu_phase_set_phase()  local
68 	/* Get our parent clock, it's the one that can adjust its rate */  in ccu_phase_set_phase()
71 		return -EINVAL;  in ccu_phase_set_phase()
76 		return -EINVAL;  in ccu_phase_set_phase()
81 		return -EINVAL;  in ccu_phase_set_phase()
86 		return -EINVAL;  in ccu_phase_set_phase()
98 		 * Since our parent clock is only a divider, and the  in ccu_phase_set_phase()
104 		 * of period we want to outphase our clock from, and  in ccu_phase_set_phase()
105 		 * the divider set by our parent clock.  in ccu_phase_set_phase()
108 		delay = DIV_ROUND_CLOSEST(degrees, step);  in ccu_phase_set_phase()
110 		delay = 0;  in ccu_phase_set_phase()
113 	spin_lock_irqsave(phase->common.lock, flags);  in ccu_phase_set_phase()
114 	reg = readl(phase->common.base + phase->common.reg);  in ccu_phase_set_phase()
115 	reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);  in ccu_phase_set_phase()
116 	writel(reg | (delay << phase->shift),  in ccu_phase_set_phase()
117 	       phase->common.base + phase->common.reg);  in ccu_phase_set_phase()
118 	spin_unlock_irqrestore(phase->common.lock, flags);  in ccu_phase_set_phase()