Lines Matching +full:reg +full:- +full:mux
8 * Adjustable factor-based clock implementation
11 #include <linux/clk-provider.h>
19 #include "clk-factors.h"
22 * DOC: basic adjustable factor-based clock
25 * prepare - clk_prepare only ensures that parents are prepared
26 * enable - clk_enable only ensures that parents are enabled
27 * rate - rate is adjustable.
28 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
29 * parent - fixed parent. No clk_set_parent support
36 #define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
38 #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit)) argument
40 #define FACTOR_SET(bit, len, reg, val) \ argument
41 (((reg) & CLRMASK(len, bit)) | (val << (bit)))
47 u32 reg; in clk_factors_recalc_rate() local
50 const struct clk_factors_config *config = factors->config; in clk_factors_recalc_rate()
53 reg = readl(factors->reg); in clk_factors_recalc_rate()
56 if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE) in clk_factors_recalc_rate()
57 n = FACTOR_GET(config->nshift, config->nwidth, reg); in clk_factors_recalc_rate()
58 if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE) in clk_factors_recalc_rate()
59 k = FACTOR_GET(config->kshift, config->kwidth, reg); in clk_factors_recalc_rate()
60 if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE) in clk_factors_recalc_rate()
61 m = FACTOR_GET(config->mshift, config->mwidth, reg); in clk_factors_recalc_rate()
62 if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE) in clk_factors_recalc_rate()
63 p = FACTOR_GET(config->pshift, config->pwidth, reg); in clk_factors_recalc_rate()
65 if (factors->recalc) { in clk_factors_recalc_rate()
74 /* get mux details from mux clk structure */ in clk_factors_recalc_rate()
75 if (factors->mux) in clk_factors_recalc_rate()
77 (reg >> factors->mux->shift) & in clk_factors_recalc_rate()
78 factors->mux->mask; in clk_factors_recalc_rate()
80 factors->recalc(&factors_req); in clk_factors_recalc_rate()
86 rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1); in clk_factors_recalc_rate()
103 .rate = req->rate, in clk_factors_determine_rate()
110 parent_rate = clk_hw_round_rate(parent, req->rate); in clk_factors_determine_rate()
115 factors->get_factors(&factors_req); in clk_factors_determine_rate()
118 if (child_rate <= req->rate && child_rate > best_child_rate) { in clk_factors_determine_rate()
126 return -EINVAL; in clk_factors_determine_rate()
128 req->best_parent_hw = best_parent; in clk_factors_determine_rate()
129 req->best_parent_rate = best; in clk_factors_determine_rate()
130 req->rate = best_child_rate; in clk_factors_determine_rate()
142 u32 reg; in clk_factors_set_rate() local
144 const struct clk_factors_config *config = factors->config; in clk_factors_set_rate()
147 factors->get_factors(&req); in clk_factors_set_rate()
149 if (factors->lock) in clk_factors_set_rate()
150 spin_lock_irqsave(factors->lock, flags); in clk_factors_set_rate()
153 reg = readl(factors->reg); in clk_factors_set_rate()
155 /* Set up the new factors - macros do not do anything if width is 0 */ in clk_factors_set_rate()
156 reg = FACTOR_SET(config->nshift, config->nwidth, reg, req.n); in clk_factors_set_rate()
157 reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k); in clk_factors_set_rate()
158 reg = FACTOR_SET(config->mshift, config->mwidth, reg, req.m); in clk_factors_set_rate()
159 reg = FACTOR_SET(config->pshift, config->pwidth, reg, req.p); in clk_factors_set_rate()
162 writel(reg, factors->reg); in clk_factors_set_rate()
167 if (factors->lock) in clk_factors_set_rate()
168 spin_unlock_irqrestore(factors->lock, flags); in clk_factors_set_rate()
181 spinlock_t *lock, void __iomem *reg, in __sunxi_factors_register() argument
187 struct clk_mux *mux = NULL; in __sunxi_factors_register() local
190 const char *clk_name = node->name; in __sunxi_factors_register()
194 /* if we have a mux, we will have >1 parents */ in __sunxi_factors_register()
201 if (data->name) in __sunxi_factors_register()
202 clk_name = data->name; in __sunxi_factors_register()
204 of_property_read_string(node, "clock-output-names", &clk_name); in __sunxi_factors_register()
211 factors->reg = reg; in __sunxi_factors_register()
212 factors->config = data->table; in __sunxi_factors_register()
213 factors->get_factors = data->getter; in __sunxi_factors_register()
214 factors->recalc = data->recalc; in __sunxi_factors_register()
215 factors->lock = lock; in __sunxi_factors_register()
218 if (data->enable) { in __sunxi_factors_register()
223 factors->gate = gate; in __sunxi_factors_register()
226 gate->reg = reg; in __sunxi_factors_register()
227 gate->bit_idx = data->enable; in __sunxi_factors_register()
228 gate->lock = factors->lock; in __sunxi_factors_register()
229 gate_hw = &gate->hw; in __sunxi_factors_register()
232 /* Add a mux if this factor clock can be muxed */ in __sunxi_factors_register()
233 if (data->mux) { in __sunxi_factors_register()
234 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); in __sunxi_factors_register()
235 if (!mux) in __sunxi_factors_register()
238 factors->mux = mux; in __sunxi_factors_register()
241 mux->reg = reg; in __sunxi_factors_register()
242 mux->shift = data->mux; in __sunxi_factors_register()
243 mux->mask = data->muxmask; in __sunxi_factors_register()
244 mux->lock = factors->lock; in __sunxi_factors_register()
245 mux_hw = &mux->hw; in __sunxi_factors_register()
251 &factors->hw, &clk_factors_ops, in __sunxi_factors_register()
266 kfree(mux); in __sunxi_factors_register()
278 void __iomem *reg) in sunxi_factors_register() argument
280 return __sunxi_factors_register(node, data, lock, reg, 0); in sunxi_factors_register()
286 void __iomem *reg) in sunxi_factors_register_critical() argument
288 return __sunxi_factors_register(node, data, lock, reg, CLK_IS_CRITICAL); in sunxi_factors_register_critical()
304 kfree(factors->mux); in sunxi_factors_unregister()
305 kfree(factors->gate); in sunxi_factors_unregister()