18 #include <linux/clk-provider.h>
23 #include "clk-factors.h"
26  * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
37 	if (req->rate > req->parent_rate)  in sun4i_a10_get_mod0_factors()
38 		req->rate = req->parent_rate;  in sun4i_a10_get_mod0_factors()
40 	div = DIV_ROUND_UP(req->parent_rate, req->rate);  in sun4i_a10_get_mod0_factors()
53 	req->rate = (req->parent_rate >> calcp) / calcm;  in sun4i_a10_get_mod0_factors()
54 	req->m = calcm - 1;  in sun4i_a10_get_mod0_factors()
55 	req->p = calcp;  in sun4i_a10_get_mod0_factors()
93 CLK_OF_DECLARE_DRIVER(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk",
98 	struct device_node *np = pdev->dev.of_node;  in sun4i_a10_mod0_clk_probe()
103 		return -ENODEV;  in sun4i_a10_mod0_clk_probe()
106 	reg = devm_ioremap_resource(&pdev->dev, r);  in sun4i_a10_mod0_clk_probe()
116 	{ .compatible = "allwinner,sun4i-a10-mod0-clk" },
122 		.name = "sun4i-a10-mod0-clk",
143 		pr_err("Could not get registers for mod0-clk: %s\n",  in sun9i_a80_mod0_setup()
144 		       node->name);  in sun9i_a80_mod0_setup()
151 CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup);
161 		pr_err("Could not get registers for a13-mbus-clk\n");  in sun5i_a13_mbus_setup()
169 CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
182 	struct clk *mmc, *mmc_parent, *clk = hw->clk;  in mmc_get_phase()
187 	u8 delay;  in mmc_get_phase()  local
189 	value = readl(phase->reg);  in mmc_get_phase()
190 	delay = (value >> phase->offset) & 0x3;  in mmc_get_phase()
192 	if (!delay)  in mmc_get_phase()
198 		return -EINVAL;  in mmc_get_phase()
203 		return -EINVAL;  in mmc_get_phase()
208 		return -EINVAL;  in mmc_get_phase()
213 		return -EINVAL;  in mmc_get_phase()
219 	return delay * step;  in mmc_get_phase()
224 	struct clk *mmc, *mmc_parent, *clk = hw->clk;  in mmc_set_phase()
229 	u8 delay;  in mmc_set_phase()  local
234 		return -EINVAL;  in mmc_set_phase()
239 		return -EINVAL;  in mmc_set_phase()
244 		return -EINVAL;  in mmc_set_phase()
249 		return -EINVAL;  in mmc_set_phase()
271 		delay = DIV_ROUND_CLOSEST(degrees, step);  in mmc_set_phase()
273 		delay = 0;  in mmc_set_phase()
276 	spin_lock_irqsave(phase->lock, flags);  in mmc_set_phase()
277 	value = readl(phase->reg);  in mmc_set_phase()
278 	value &= ~GENMASK(phase->offset + 3, phase->offset);  in mmc_set_phase()
279 	value |= delay << phase->offset;  in mmc_set_phase()
280 	writel(value, phase->reg);  in mmc_set_phase()
281 	spin_unlock_irqrestore(phase->lock, flags);  in mmc_set_phase()
292  * sunxi_mmc_setup - Common setup function for mmc module clocks
309 		pr_err("Couldn't map the %s clock registers\n", node->name);  in sunxi_mmc_setup()
317 	clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);  in sunxi_mmc_setup()
318 	if (!clk_data->clks)  in sunxi_mmc_setup()
321 	clk_data->clk_num = 3;  in sunxi_mmc_setup()
322 	clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);  in sunxi_mmc_setup()
323 	if (!clk_data->clks[0])  in sunxi_mmc_setup()
326 	parent = __clk_get_name(clk_data->clks[0]);  in sunxi_mmc_setup()
329 		struct clk_init_data init = {  in sunxi_mmc_setup()  local
340 		phase->hw.init = &init;  in sunxi_mmc_setup()
341 		phase->reg = reg;  in sunxi_mmc_setup()
342 		phase->lock = lock;  in sunxi_mmc_setup()
345 			phase->offset = 8;  in sunxi_mmc_setup()
347 			phase->offset = 20;  in sunxi_mmc_setup()
349 		if (of_property_read_string_index(node, "clock-output-names",  in sunxi_mmc_setup()
350 						  i, &init.name))  in sunxi_mmc_setup()
351 			init.name = node->name;  in sunxi_mmc_setup()
353 		clk_data->clks[i] = clk_register(NULL, &phase->hw);  in sunxi_mmc_setup()
354 		if (IS_ERR(clk_data->clks[i])) {  in sunxi_mmc_setup()
365 	kfree(clk_data->clks);  in sunxi_mmc_setup()
376 CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup);
384 CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);