Lines Matching +full:clk +full:- +full:div
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
22 #include <linux/reset-controller.h>
27 #include "clk-factors.h"
35 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
43 u8 div; in sun4i_get_pll1_factors() local
46 div = req->rate / 6000000; in sun4i_get_pll1_factors()
47 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
50 req->m = 0; in sun4i_get_pll1_factors()
53 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
54 req->rate == 54000000) in sun4i_get_pll1_factors()
55 req->k = 1; in sun4i_get_pll1_factors()
57 req->k = 0; in sun4i_get_pll1_factors()
60 if (div < 10) in sun4i_get_pll1_factors()
61 req->p = 3; in sun4i_get_pll1_factors()
63 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ in sun4i_get_pll1_factors()
64 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
65 req->p = 2; in sun4i_get_pll1_factors()
68 * of divs between 40-62 */ in sun4i_get_pll1_factors()
69 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
70 req->p = 1; in sun4i_get_pll1_factors()
74 req->p = 0; in sun4i_get_pll1_factors()
77 div <<= req->p; in sun4i_get_pll1_factors()
78 div /= (req->k + 1); in sun4i_get_pll1_factors()
79 req->n = div / 4; in sun4i_get_pll1_factors()
83 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
94 u32 freq_mhz = req->rate / 1000000; in sun6i_a31_get_pll1_factors()
95 u32 parent_freq_mhz = req->parent_rate / 1000000; in sun6i_a31_get_pll1_factors()
109 req->rate = freq_mhz * 1000000; in sun6i_a31_get_pll1_factors()
113 req->k = 3; in sun6i_a31_get_pll1_factors()
116 req->k = 2; in sun6i_a31_get_pll1_factors()
119 req->k = 1; in sun6i_a31_get_pll1_factors()
122 req->k = 0; in sun6i_a31_get_pll1_factors()
133 req->m = 2; in sun6i_a31_get_pll1_factors()
139 req->m = 3; in sun6i_a31_get_pll1_factors()
142 req->m = 1; in sun6i_a31_get_pll1_factors()
145 req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz) in sun6i_a31_get_pll1_factors()
146 - 1; in sun6i_a31_get_pll1_factors()
152 if ((req->n + 1) > 31 && (req->m + 1) > 1) { in sun6i_a31_get_pll1_factors()
153 req->n = (req->n + 1) / 2 - 1; in sun6i_a31_get_pll1_factors()
154 req->m = (req->m + 1) / 2 - 1; in sun6i_a31_get_pll1_factors()
159 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
167 u8 div; in sun8i_a23_get_pll1_factors() local
170 div = req->rate / 6000000; in sun8i_a23_get_pll1_factors()
171 req->rate = 6000000 * div; in sun8i_a23_get_pll1_factors()
174 req->m = 0; in sun8i_a23_get_pll1_factors()
177 if (req->rate >= 768000000 || req->rate == 42000000 || in sun8i_a23_get_pll1_factors()
178 req->rate == 54000000) in sun8i_a23_get_pll1_factors()
179 req->k = 1; in sun8i_a23_get_pll1_factors()
181 req->k = 0; in sun8i_a23_get_pll1_factors()
184 if (div < 20 || (div < 32 && (div & 1))) in sun8i_a23_get_pll1_factors()
185 req->p = 2; in sun8i_a23_get_pll1_factors()
188 * of divs between 40-62 */ in sun8i_a23_get_pll1_factors()
189 else if (div < 40 || (div < 64 && (div & 2))) in sun8i_a23_get_pll1_factors()
190 req->p = 1; in sun8i_a23_get_pll1_factors()
194 req->p = 0; in sun8i_a23_get_pll1_factors()
197 div <<= req->p; in sun8i_a23_get_pll1_factors()
198 div /= (req->k + 1); in sun8i_a23_get_pll1_factors()
199 req->n = div / 4 - 1; in sun8i_a23_get_pll1_factors()
203 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
211 u8 div; in sun4i_get_pll5_factors() local
214 div = req->rate / req->parent_rate; in sun4i_get_pll5_factors()
215 req->rate = req->parent_rate * div; in sun4i_get_pll5_factors()
217 if (div < 31) in sun4i_get_pll5_factors()
218 req->k = 0; in sun4i_get_pll5_factors()
219 else if (div / 2 < 31) in sun4i_get_pll5_factors()
220 req->k = 1; in sun4i_get_pll5_factors()
221 else if (div / 3 < 31) in sun4i_get_pll5_factors()
222 req->k = 2; in sun4i_get_pll5_factors()
224 req->k = 3; in sun4i_get_pll5_factors()
226 req->n = DIV_ROUND_UP(div, (req->k + 1)); in sun4i_get_pll5_factors()
230 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
238 u8 div; in sun6i_a31_get_pll6_factors() local
241 div = req->rate / req->parent_rate; in sun6i_a31_get_pll6_factors()
242 req->rate = req->parent_rate * div; in sun6i_a31_get_pll6_factors()
244 req->k = div / 32; in sun6i_a31_get_pll6_factors()
245 if (req->k > 3) in sun6i_a31_get_pll6_factors()
246 req->k = 3; in sun6i_a31_get_pll6_factors()
248 req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1; in sun6i_a31_get_pll6_factors()
252 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
259 u32 div; in sun5i_a13_get_ahb_factors() local
262 if (req->parent_rate < req->rate) in sun5i_a13_get_ahb_factors()
263 req->rate = req->parent_rate; in sun5i_a13_get_ahb_factors()
269 if (req->rate < 8000) in sun5i_a13_get_ahb_factors()
270 req->rate = 8000; in sun5i_a13_get_ahb_factors()
271 if (req->rate > 300000000) in sun5i_a13_get_ahb_factors()
272 req->rate = 300000000; in sun5i_a13_get_ahb_factors()
274 div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate)); in sun5i_a13_get_ahb_factors()
277 if (div > 3) in sun5i_a13_get_ahb_factors()
278 div = 3; in sun5i_a13_get_ahb_factors()
280 req->rate = req->parent_rate >> div; in sun5i_a13_get_ahb_factors()
282 req->p = div; in sun5i_a13_get_ahb_factors()
288 * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
298 u8 div, calcp, calcm = 1; in sun6i_get_ahb1_factors() local
304 if (req->parent_rate && req->rate > req->parent_rate) in sun6i_get_ahb1_factors()
305 req->rate = req->parent_rate; in sun6i_get_ahb1_factors()
307 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_get_ahb1_factors()
309 /* calculate pre-divider if parent is pll6 */ in sun6i_get_ahb1_factors()
310 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) { in sun6i_get_ahb1_factors()
311 if (div < 4) in sun6i_get_ahb1_factors()
313 else if (div / 2 < 4) in sun6i_get_ahb1_factors()
315 else if (div / 4 < 4) in sun6i_get_ahb1_factors()
320 calcm = DIV_ROUND_UP(div, 1 << calcp); in sun6i_get_ahb1_factors()
322 calcp = __roundup_pow_of_two(div); in sun6i_get_ahb1_factors()
326 req->rate = (req->parent_rate / calcm) >> calcp; in sun6i_get_ahb1_factors()
327 req->p = calcp; in sun6i_get_ahb1_factors()
328 req->m = calcm - 1; in sun6i_get_ahb1_factors()
332 * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
337 req->rate = req->parent_rate; in sun6i_ahb1_recalc()
339 /* apply pre-divider first if parent is pll6 */ in sun6i_ahb1_recalc()
340 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) in sun6i_ahb1_recalc()
341 req->rate /= req->m + 1; in sun6i_ahb1_recalc()
343 /* clk divider */ in sun6i_ahb1_recalc()
344 req->rate >>= req->p; in sun6i_ahb1_recalc()
348 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
356 int div; in sun4i_get_apb1_factors() local
358 if (req->parent_rate < req->rate) in sun4i_get_apb1_factors()
359 req->rate = req->parent_rate; in sun4i_get_apb1_factors()
361 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_get_apb1_factors()
364 if (div > 32) in sun4i_get_apb1_factors()
367 if (div <= 4) in sun4i_get_apb1_factors()
369 else if (div <= 8) in sun4i_get_apb1_factors()
371 else if (div <= 16) in sun4i_get_apb1_factors()
376 calcm = (div >> calcp) - 1; in sun4i_get_apb1_factors()
378 req->rate = (req->parent_rate >> calcp) / (calcm + 1); in sun4i_get_apb1_factors()
379 req->m = calcm; in sun4i_get_apb1_factors()
380 req->p = calcp; in sun4i_get_apb1_factors()
387 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
394 u8 div, calcm, calcp; in sun7i_a20_get_out_factors() local
398 if (req->rate > req->parent_rate) in sun7i_a20_get_out_factors()
399 req->rate = req->parent_rate; in sun7i_a20_get_out_factors()
401 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun7i_a20_get_out_factors()
403 if (div < 32) in sun7i_a20_get_out_factors()
405 else if (div / 2 < 32) in sun7i_a20_get_out_factors()
407 else if (div / 4 < 32) in sun7i_a20_get_out_factors()
412 calcm = DIV_ROUND_UP(div, 1 << calcp); in sun7i_a20_get_out_factors()
414 req->rate = (req->parent_rate >> calcp) / calcm; in sun7i_a20_get_out_factors()
415 req->m = calcm - 1; in sun7i_a20_get_out_factors()
416 req->p = calcp; in sun7i_a20_get_out_factors()
420 * sunxi_factors_clk_setup() - Setup function for factor clocks
564 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, in sunxi_factors_clk_setup()
571 pr_err("Could not get registers for factors-clk: %s\n", in sunxi_factors_clk_setup()
572 node->name); in sunxi_factors_clk_setup()
583 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
590 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
597 CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
604 CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
611 CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
618 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
625 CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
632 CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
637 * sunxi_mux_clk_setup() - Setup function for muxes
658 static struct clk * __init sunxi_mux_clk_setup(struct device_node *node, in sunxi_mux_clk_setup()
662 struct clk *clk; in sunxi_mux_clk_setup() local
663 const char *clk_name = node->name; in sunxi_mux_clk_setup()
670 pr_err("Could not map registers for mux-clk: %pOF\n", node); in sunxi_mux_clk_setup()
675 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_mux_clk_setup()
676 pr_err("%s: could not read clock-output-names from \"%pOF\"\n", in sunxi_mux_clk_setup()
681 clk = clk_register_mux(NULL, clk_name, parents, i, in sunxi_mux_clk_setup()
683 data->shift, SUNXI_MUX_GATE_WIDTH, in sunxi_mux_clk_setup()
686 if (IS_ERR(clk)) { in sunxi_mux_clk_setup()
688 clk_name, PTR_ERR(clk)); in sunxi_mux_clk_setup()
692 if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) { in sunxi_mux_clk_setup()
695 clk_unregister_divider(clk); in sunxi_mux_clk_setup()
699 return clk; in sunxi_mux_clk_setup()
710 CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
717 CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
724 CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
729 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
746 { .val = 0, .div = 1 },
747 { .val = 1, .div = 2 },
748 { .val = 2, .div = 3 },
749 { .val = 3, .div = 4 },
750 { .val = 4, .div = 4 },
751 { .val = 5, .div = 4 },
752 { .val = 6, .div = 4 },
753 { .val = 7, .div = 4 },
769 { .val = 0, .div = 2 },
770 { .val = 1, .div = 2 },
771 { .val = 2, .div = 4 },
772 { .val = 3, .div = 8 },
786 struct clk *clk; in sunxi_divider_clk_setup() local
787 const char *clk_name = node->name; in sunxi_divider_clk_setup()
793 pr_err("Could not map registers for mux-clk: %pOF\n", node); in sunxi_divider_clk_setup()
799 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_divider_clk_setup()
800 pr_err("%s: could not read clock-output-names from \"%pOF\"\n", in sunxi_divider_clk_setup()
805 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, in sunxi_divider_clk_setup()
806 reg, data->shift, data->width, in sunxi_divider_clk_setup()
807 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, in sunxi_divider_clk_setup()
808 data->table, &clk_lock); in sunxi_divider_clk_setup()
809 if (IS_ERR(clk)) { in sunxi_divider_clk_setup()
811 __func__, clk_name, PTR_ERR(clk)); in sunxi_divider_clk_setup()
815 if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) { in sunxi_divider_clk_setup()
821 if (clk_register_clkdev(clk, clk_name, NULL)) { in sunxi_divider_clk_setup()
828 clk_unregister_divider(clk); in sunxi_divider_clk_setup()
838 CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
845 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
852 CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
859 CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
865 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
895 u8 pow; /* is it power-of-two based? */
898 } div[SUNXI_DIVS_MAX_QTY]; member
902 { .val = 0, .div = 6, },
903 { .val = 1, .div = 12, },
904 { .val = 2, .div = 18, },
905 { .val = 3, .div = 24, },
912 .div = {
923 .div = {
934 .div = {
941 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
945 * | ___divisor 1---|----> to consumer
946 * parent >--| pll___/___divisor 2---|----> to consumer
951 static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node, in sunxi_divs_clk_setup()
957 struct clk **clks, *pclk; in sunxi_divs_clk_setup()
963 struct factors_data factors = *data->factors; in sunxi_divs_clk_setup()
970 if (data->ndivs) in sunxi_divs_clk_setup()
971 ndivs = data->ndivs; in sunxi_divs_clk_setup()
975 if (data->div[i].self) { in sunxi_divs_clk_setup()
976 of_property_read_string_index(node, "clock-output-names", in sunxi_divs_clk_setup()
981 /* If we don't have a .self clk use the first output-name up to '_' */ in sunxi_divs_clk_setup()
985 of_property_read_string_index(node, "clock-output-names", in sunxi_divs_clk_setup()
989 derived_name = kstrndup(clk_name, endp - clk_name, in sunxi_divs_clk_setup()
1009 pr_err("Could not map registers for divs-clk: %pOF\n", node); in sunxi_divs_clk_setup()
1021 clk_data->clks = clks; in sunxi_divs_clk_setup()
1028 if (of_property_read_string_index(node, "clock-output-names", in sunxi_divs_clk_setup()
1033 if (data->div[i].self) { in sunxi_divs_clk_setup()
1034 clk_data->clks[i] = pclk; in sunxi_divs_clk_setup()
1043 if (data->div[i].gate) { in sunxi_divs_clk_setup()
1048 gate->reg = reg; in sunxi_divs_clk_setup()
1049 gate->bit_idx = data->div[i].gate; in sunxi_divs_clk_setup()
1050 gate->lock = &clk_lock; in sunxi_divs_clk_setup()
1052 gate_hw = &gate->hw; in sunxi_divs_clk_setup()
1056 if (data->div[i].fixed) { in sunxi_divs_clk_setup()
1061 fix_factor->mult = 1; in sunxi_divs_clk_setup()
1062 fix_factor->div = data->div[i].fixed; in sunxi_divs_clk_setup()
1064 rate_hw = &fix_factor->hw; in sunxi_divs_clk_setup()
1071 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; in sunxi_divs_clk_setup()
1073 divider->reg = reg; in sunxi_divs_clk_setup()
1074 divider->shift = data->div[i].shift; in sunxi_divs_clk_setup()
1075 divider->width = SUNXI_DIVISOR_WIDTH; in sunxi_divs_clk_setup()
1076 divider->flags = flags; in sunxi_divs_clk_setup()
1077 divider->lock = &clk_lock; in sunxi_divs_clk_setup()
1078 divider->table = data->div[i].table; in sunxi_divs_clk_setup()
1080 rate_hw = ÷r->hw; in sunxi_divs_clk_setup()
1091 (data->div[i].critical ? in sunxi_divs_clk_setup()
1094 WARN_ON(IS_ERR(clk_data->clks[i])); in sunxi_divs_clk_setup()
1098 clk_data->clk_num = i; in sunxi_divs_clk_setup()
1122 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
1129 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1136 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
1148 if (req->rate > req->parent_rate) in sun6i_display_factors()
1149 req->rate = req->parent_rate; in sun6i_display_factors()
1151 m = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_display_factors()
1153 req->rate = req->parent_rate / m; in sun6i_display_factors()
1154 req->m = m - 1; in sun6i_display_factors()
1174 CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk",