Lines Matching +full:oscillator +full:- +full:stable +full:- +full:time
2 * clk-dfll.c - Tegra DFLL clock source common code
4 * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
20 * "CL-DVFS". To try to avoid confusion, this code refers to them
26 * DFLL can be operated in either open-loop mode or closed-loop mode.
27 * In open-loop mode, the DFLL generates an output clock appropriate
28 * to the supply voltage. In closed-loop mode, when configured with a
34 * CPU cycle time will vary. This has implications for
35 * performance-measurement code and any code that relies on the CPU
36 * cycle time to delay for a certain length of time.
41 #include <linux/clk-provider.h>
57 #include "clk-dfll.h"
61 * DFLL control registers - access via dfll_{readl,writel}
97 #define FORCE_MIN -2048
147 * I2C output control registers - access via dfll_i2c_{readl,writel}
179 * Integrated I2C controller registers - relative to td->i2c_controller_base
199 * integrates the DVCO counter over - used for debug rate monitoring and
214 * enum dfll_ctrl_mode - DFLL hardware operating mode
215 * @DFLL_UNINITIALIZED: (uninitialized state - not in hardware bitfield)
232 * enum dfll_tune_range - voltage range that the driver believes it's in
234 * @DFLL_TUNE_LOW: DFLL in the low-voltage range (or open-loop mode)
247 * struct dfll_rate_req - target DFLL rate request data
325 return __raw_readl(td->base + offs); in dfll_readl()
331 __raw_writel(val, td->base + offs); in dfll_writel()
339 /* I2C output control registers - for addresses above DFLL_I2C_CFG */
343 return __raw_readl(td->i2c_base + offs); in dfll_i2c_readl()
348 __raw_writel(val, td->i2c_base + offs); in dfll_i2c_writel()
357 * dfll_is_running - is the DFLL currently generating a clock?
365 return td->mode >= DFLL_OPEN_LOOP; in dfll_is_running()
373 * tegra_dfll_runtime_resume - enable all clocks needed by the DFLL
386 ret = clk_enable(td->ref_clk); in tegra_dfll_runtime_resume()
392 ret = clk_enable(td->soc_clk); in tegra_dfll_runtime_resume()
395 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
399 ret = clk_enable(td->i2c_clk); in tegra_dfll_runtime_resume()
402 clk_disable(td->soc_clk); in tegra_dfll_runtime_resume()
403 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
412 * tegra_dfll_runtime_suspend - disable all clocks needed by the DFLL
422 clk_disable(td->ref_clk); in tegra_dfll_runtime_suspend()
423 clk_disable(td->soc_clk); in tegra_dfll_runtime_suspend()
424 clk_disable(td->i2c_clk); in tegra_dfll_runtime_suspend()
431 * DFLL tuning operations (per-voltage-range tuning settings)
435 * dfll_tune_low - tune to DFLL and CPU settings valid for any voltage
438 * Tune the DFLL oscillator parameters and the CPU clock shaper for
439 * the low-voltage range. These settings are valid for any voltage,
444 td->tune_range = DFLL_TUNE_LOW; in dfll_tune_low()
446 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0); in dfll_tune_low()
447 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1); in dfll_tune_low()
450 if (td->soc->set_clock_trimmers_low) in dfll_tune_low()
451 td->soc->set_clock_trimmers_low(); in dfll_tune_low()
459 * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate
477 * dfll_set_mode - change the DFLL control mode
481 * Change the DFLL's operating mode between disabled, open-loop mode,
482 * and closed-loop mode, or vice versa.
487 td->mode = mode; in dfll_set_mode()
488 dfll_writel(td, mode - 1, DFLL_CTRL); in dfll_set_mode()
493 * DFLL-to-I2C controller interface
497 * dfll_i2c_set_output_enabled - enable/disable I2C PMIC voltage requests
522 * dfll_load_lut - load the voltage lookup table
525 * Load the voltage-to-PMIC register value lookup table into the DFLL
526 * IP block memory. Look-up tables can be loaded at any time.
534 if (i < td->lut_min) in dfll_load_i2c_lut()
535 lut_index = td->lut_min; in dfll_load_i2c_lut()
536 else if (i > td->lut_max) in dfll_load_i2c_lut()
537 lut_index = td->lut_max; in dfll_load_i2c_lut()
541 val = regulator_list_hardware_vsel(td->vdd_reg, in dfll_load_i2c_lut()
542 td->i2c_lut[lut_index]); in dfll_load_i2c_lut()
543 __raw_writel(val, td->lut_base + i * 4); in dfll_load_i2c_lut()
550 * dfll_init_i2c_if - set up the DFLL's DFLL-I2C interface
553 * During DFLL driver initialization, program the DFLL-I2C interface
556 * voltage-set commands, which are then passed to the DFLL's internal
563 if (td->i2c_slave_addr > 0x7f) { in dfll_init_i2c_if()
564 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT; in dfll_init_i2c_if()
567 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT; in dfll_init_i2c_if()
573 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR); in dfll_init_i2c_if()
575 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8); in dfll_init_i2c_if()
577 val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT; in dfll_init_i2c_if()
581 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR); in dfll_init_i2c_if()
586 * dfll_init_out_if - prepare DFLL-to-PMIC interface
597 td->lut_min = 0; in dfll_init_out_if()
598 td->lut_max = td->i2c_lut_size - 1; in dfll_init_out_if()
599 td->lut_safe = td->lut_min + 1; in dfll_init_out_if()
602 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | in dfll_init_out_if()
603 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | in dfll_init_out_if()
604 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); in dfll_init_out_if()
622 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
628 * to the integrator during rate changes. Returns -ENOENT if a suitable
636 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in find_lut_index_for_rate()
643 for (i = 0; i < td->i2c_lut_size; i++) { in find_lut_index_for_rate()
644 if (regulator_list_voltage(td->vdd_reg, td->i2c_lut[i]) == uv) in find_lut_index_for_rate()
648 return -ENOENT; in find_lut_index_for_rate()
652 * dfll_calculate_rate_request - calculate DFLL parameters for a given rate
654 * @req: DFLL-rate-request structure
657 * Populate the DFLL-rate-request record @req fields with the scale_bits
659 * success, or -EINVAL if the requested rate in req->rate is too high
674 req->scale_bits = DFLL_FREQ_REQ_SCALE_MAX - 1; in dfll_calculate_rate_request()
675 if (rate < td->dvco_rate_min) { in dfll_calculate_rate_request()
679 td->dvco_rate_min / 1000); in dfll_calculate_rate_request()
681 dev_err(td->dev, "%s: Rate %lu is too low\n", in dfll_calculate_rate_request()
683 return -EINVAL; in dfll_calculate_rate_request()
685 req->scale_bits = scale - 1; in dfll_calculate_rate_request()
686 rate = td->dvco_rate_min; in dfll_calculate_rate_request()
690 val = DVCO_RATE_TO_MULT(rate, td->ref_rate); in dfll_calculate_rate_request()
692 dev_err(td->dev, "%s: Rate %lu is above dfll range\n", in dfll_calculate_rate_request()
694 return -EINVAL; in dfll_calculate_rate_request()
696 req->mult_bits = val; in dfll_calculate_rate_request()
697 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate); in dfll_calculate_rate_request()
698 req->rate = dfll_scale_dvco_rate(req->scale_bits, in dfll_calculate_rate_request()
699 req->dvco_target_rate); in dfll_calculate_rate_request()
700 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate); in dfll_calculate_rate_request()
701 if (req->lut_index < 0) in dfll_calculate_rate_request()
702 return req->lut_index; in dfll_calculate_rate_request()
708 * dfll_set_frequency_request - start the frequency change operation
713 * frequency represented by @req. DFLL must be in closed-loop mode.
720 int coef = 128; /* FIXME: td->cg_scale? */; in dfll_set_frequency_request()
722 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; in dfll_set_frequency_request()
725 val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT; in dfll_set_frequency_request()
726 val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT; in dfll_set_frequency_request()
736 * tegra_dfll_request_rate - set the next rate for the DFLL to tune to
741 * settings. In closed-loop mode, update new settings immediately to
744 * -EPERM if the DFLL driver has not yet been initialized, or -EINVAL
752 if (td->mode == DFLL_UNINITIALIZED) { in dfll_request_rate()
753 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n", in dfll_request_rate()
754 __func__, mode_name[td->mode]); in dfll_request_rate()
755 return -EPERM; in dfll_request_rate()
762 td->last_unrounded_rate = rate; in dfll_request_rate()
763 td->last_req = req; in dfll_request_rate()
765 if (td->mode == DFLL_CLOSED_LOOP) in dfll_request_rate()
766 dfll_set_frequency_request(td, &td->last_req); in dfll_request_rate()
772 * DFLL enable/disable & open-loop <-> closed-loop transitions
776 * dfll_disable - switch from open-loop mode to disabled mode
780 * or -EPERM if the DFLL is not currently in open-loop mode.
784 if (td->mode != DFLL_OPEN_LOOP) { in dfll_disable()
785 dev_err(td->dev, "cannot disable DFLL in %s mode\n", in dfll_disable()
786 mode_name[td->mode]); in dfll_disable()
787 return -EINVAL; in dfll_disable()
791 pm_runtime_put_sync(td->dev); in dfll_disable()
797 * dfll_enable - switch a disabled DFLL to open-loop mode
801 * or -EPERM if the DFLL is not currently disabled.
805 if (td->mode != DFLL_DISABLED) { in dfll_enable()
806 dev_err(td->dev, "cannot enable DFLL in %s mode\n", in dfll_enable()
807 mode_name[td->mode]); in dfll_enable()
808 return -EPERM; in dfll_enable()
811 pm_runtime_get_sync(td->dev); in dfll_enable()
818 * dfll_set_open_loop_config - prepare to switch to open-loop mode
821 * Prepare to switch the DFLL to open-loop mode. This switches the
822 * DFLL to the low-voltage tuning range, ensures that I2C output
824 * The DFLL's low-voltage tuning range parameters must be
825 * characterized to keep the downstream device stable at any DVCO
833 if (td->tune_range != DFLL_TUNE_LOW) in dfll_set_open_loop_config()
844 * tegra_dfll_lock - switch from open-loop to closed-loop mode
848 * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the
849 * DFLL is not currently in open-loop mode.
853 struct dfll_rate_req *req = &td->last_req; in dfll_lock()
855 switch (td->mode) { in dfll_lock()
860 if (req->rate == 0) { in dfll_lock()
861 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n", in dfll_lock()
863 return -EINVAL; in dfll_lock()
872 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_lock()
873 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n", in dfll_lock()
874 __func__, mode_name[td->mode]); in dfll_lock()
875 return -EPERM; in dfll_lock()
880 * tegra_dfll_unlock - switch from closed-loop to open-loop mode
884 * or -EPERM if the DFLL is not currently in open-loop mode.
888 switch (td->mode) { in dfll_unlock()
899 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_unlock()
900 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n", in dfll_unlock()
901 __func__, mode_name[td->mode]); in dfll_unlock()
902 return -EPERM; in dfll_unlock()
953 return td->last_unrounded_rate; in dfll_clk_recalc_rate()
956 /* Must use determine_rate since it allows for rates exceeding 2^31-1 */
964 ret = dfll_calculate_rate_request(td, &req, clk_req->rate); in dfll_clk_determine_rate()
1000 * dfll_register_clk - register the DFLL output clock with the clock framework
1004 * the DFLL driver as an OF clock provider. Returns 0 upon success or -EINVAL
1005 * or -ENOMEM upon failure.
1011 dfll_clk_init_data.name = td->output_clock_name; in dfll_register_clk()
1012 td->dfll_clk_hw.init = &dfll_clk_init_data; in dfll_register_clk()
1014 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw); in dfll_register_clk()
1015 if (IS_ERR(td->dfll_clk)) { in dfll_register_clk()
1016 dev_err(td->dev, "DFLL clock registration error\n"); in dfll_register_clk()
1017 return -EINVAL; in dfll_register_clk()
1020 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get, in dfll_register_clk()
1021 td->dfll_clk); in dfll_register_clk()
1023 dev_err(td->dev, "of_clk_add_provider() failed\n"); in dfll_register_clk()
1025 clk_unregister(td->dfll_clk); in dfll_register_clk()
1033 * dfll_unregister_clk - unregister the DFLL output clock
1041 of_clk_del_provider(td->dev->of_node); in dfll_unregister_clk()
1042 clk_unregister(td->dfll_clk); in dfll_unregister_clk()
1043 td->dfll_clk = NULL; in dfll_unregister_clk()
1056 * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
1070 * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
1074 * internal monitoring hardware. This works in both open-loop and
1075 * closed-loop mode, and takes the output scaler setting into account.
1092 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate); in dfll_read_monitor_rate()
1122 *val = (td->mode == DFLL_CLOSED_LOOP); in attr_lock_get()
1155 struct tegra_dfll *td = s->private; in attr_registers_show()
1177 __raw_readl(td->i2c_controller_base + offs)); in attr_registers_show()
1182 __raw_readl(td->lut_base + offs)); in attr_registers_show()
1189 return single_open(file, attr_registers_show, inode->i_private); in attr_registers_open()
1203 if (!td || (td->mode == DFLL_UNINITIALIZED)) in dfll_debug_init()
1207 td->debugfs_dir = root; in dfll_debug_init()
1224 * dfll_set_default_params - program non-output related DFLL parameters
1235 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32); in dfll_set_default_params()
1239 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) | in dfll_set_default_params()
1240 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) | in dfll_set_default_params()
1241 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) | in dfll_set_default_params()
1242 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | in dfll_set_default_params()
1243 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0); in dfll_set_default_params()
1247 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL); in dfll_set_default_params()
1252 * dfll_init_clks - clk_get() the DFLL source clocks
1261 td->ref_clk = devm_clk_get(td->dev, "ref"); in dfll_init_clks()
1262 if (IS_ERR(td->ref_clk)) { in dfll_init_clks()
1263 dev_err(td->dev, "missing ref clock\n"); in dfll_init_clks()
1264 return PTR_ERR(td->ref_clk); in dfll_init_clks()
1267 td->soc_clk = devm_clk_get(td->dev, "soc"); in dfll_init_clks()
1268 if (IS_ERR(td->soc_clk)) { in dfll_init_clks()
1269 dev_err(td->dev, "missing soc clock\n"); in dfll_init_clks()
1270 return PTR_ERR(td->soc_clk); in dfll_init_clks()
1273 td->i2c_clk = devm_clk_get(td->dev, "i2c"); in dfll_init_clks()
1274 if (IS_ERR(td->i2c_clk)) { in dfll_init_clks()
1275 dev_err(td->dev, "missing i2c clock\n"); in dfll_init_clks()
1276 return PTR_ERR(td->i2c_clk); in dfll_init_clks()
1278 td->i2c_clk_rate = clk_get_rate(td->i2c_clk); in dfll_init_clks()
1284 * dfll_init - Prepare the DFLL IP block for use
1296 td->ref_rate = clk_get_rate(td->ref_clk); in dfll_init()
1297 if (td->ref_rate != REF_CLOCK_RATE) { in dfll_init()
1298 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu", in dfll_init()
1299 td->ref_rate, REF_CLOCK_RATE); in dfll_init()
1300 return -EINVAL; in dfll_init()
1303 reset_control_deassert(td->dvco_rst); in dfll_init()
1305 ret = clk_prepare(td->ref_clk); in dfll_init()
1307 dev_err(td->dev, "failed to prepare ref_clk\n"); in dfll_init()
1311 ret = clk_prepare(td->soc_clk); in dfll_init()
1313 dev_err(td->dev, "failed to prepare soc_clk\n"); in dfll_init()
1317 ret = clk_prepare(td->i2c_clk); in dfll_init()
1319 dev_err(td->dev, "failed to prepare i2c_clk\n"); in dfll_init()
1323 td->last_unrounded_rate = 0; in dfll_init()
1325 pm_runtime_enable(td->dev); in dfll_init()
1326 pm_runtime_get_sync(td->dev); in dfll_init()
1331 if (td->soc->init_clock_trimmers) in dfll_init()
1332 td->soc->init_clock_trimmers(); in dfll_init()
1338 pm_runtime_put_sync(td->dev); in dfll_init()
1343 clk_unprepare(td->soc_clk); in dfll_init()
1345 clk_unprepare(td->ref_clk); in dfll_init()
1347 reset_control_assert(td->dvco_rst); in dfll_init()
1357 * Find a PMIC voltage register-to-voltage mapping for the given voltage.
1364 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_exact()
1366 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_exact()
1374 dev_err(td->dev, "no voltage map entry for %d uV\n", uV); in find_vdd_map_entry_exact()
1375 return -EINVAL; in find_vdd_map_entry_exact()
1379 * Find a PMIC voltage register-to-voltage mapping for the given voltage,
1386 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_min()
1388 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_min()
1396 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV); in find_vdd_map_entry_min()
1397 return -EINVAL; in find_vdd_map_entry_min()
1401 * dfll_build_i2c_lut - build the I2C voltage register lookup table
1404 * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with
1406 * This function builds the look-up table based on the OPP table provided by
1407 * the soc-specific platform driver (td->soc->opp_dev) and the PMIC
1408 * register-to-voltage mapping queried from the regulator framework.
1410 * On success, fills in td->i2c_lut and returns 0, or -err on failure.
1414 int ret = -EINVAL; in dfll_build_i2c_lut()
1422 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); in dfll_build_i2c_lut()
1424 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); in dfll_build_i2c_lut()
1430 v = td->soc->cvb->min_millivolts * 1000; in dfll_build_i2c_lut()
1434 td->i2c_lut[0] = lut; in dfll_build_i2c_lut()
1437 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in dfll_build_i2c_lut()
1442 if (v_opp <= td->soc->cvb->min_millivolts * 1000) in dfll_build_i2c_lut()
1443 td->dvco_rate_min = dev_pm_opp_get_freq(opp); in dfll_build_i2c_lut()
1448 v += max(1, (v_max - v) / (MAX_DFLL_VOLTAGES - j)); in dfll_build_i2c_lut()
1455 if (selector != td->i2c_lut[j - 1]) in dfll_build_i2c_lut()
1456 td->i2c_lut[j++] = selector; in dfll_build_i2c_lut()
1459 v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp; in dfll_build_i2c_lut()
1463 if (selector != td->i2c_lut[j - 1]) in dfll_build_i2c_lut()
1464 td->i2c_lut[j++] = selector; in dfll_build_i2c_lut()
1469 td->i2c_lut_size = j; in dfll_build_i2c_lut()
1471 if (!td->dvco_rate_min) in dfll_build_i2c_lut()
1472 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n", in dfll_build_i2c_lut()
1473 td->soc->cvb->min_millivolts); in dfll_build_i2c_lut()
1482 * read_dt_param - helper function for reading required parameters from the DT
1493 int err = of_property_read_u32(td->dev->of_node, param, dest); in read_dt_param()
1496 dev_err(td->dev, "failed to read DT parameter %s: %d\n", in read_dt_param()
1505 * dfll_fetch_i2c_params - query PMIC I2C params from DT & regulator subsystem
1510 * Returns 0 on success or -err on failure.
1520 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate)) in dfll_fetch_i2c_params()
1521 return -EINVAL; in dfll_fetch_i2c_params()
1523 regmap = regulator_get_regmap(td->vdd_reg); in dfll_fetch_i2c_params()
1527 td->i2c_slave_addr = i2c_client->addr; in dfll_fetch_i2c_params()
1529 ret = regulator_get_hardware_vsel_register(td->vdd_reg, in dfll_fetch_i2c_params()
1533 dev_err(td->dev, in dfll_fetch_i2c_params()
1535 return -EINVAL; in dfll_fetch_i2c_params()
1537 td->i2c_reg = vsel_reg; in dfll_fetch_i2c_params()
1541 dev_err(td->dev, "couldn't build I2C LUT\n"); in dfll_fetch_i2c_params()
1549 * dfll_fetch_common_params - read DFLL parameters from the device tree
1553 * Returns 0 on success or -EINVAL on any failure.
1559 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl); in dfll_fetch_common_params()
1560 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate); in dfll_fetch_common_params()
1561 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode); in dfll_fetch_common_params()
1562 ok &= read_dt_param(td, "nvidia,cf", &td->cf); in dfll_fetch_common_params()
1563 ok &= read_dt_param(td, "nvidia,ci", &td->ci); in dfll_fetch_common_params()
1564 ok &= read_dt_param(td, "nvidia,cg", &td->cg); in dfll_fetch_common_params()
1565 td->cg_scale = of_property_read_bool(td->dev->of_node, in dfll_fetch_common_params()
1566 "nvidia,cg-scale"); in dfll_fetch_common_params()
1568 if (of_property_read_string(td->dev->of_node, "clock-output-names", in dfll_fetch_common_params()
1569 &td->output_clock_name)) { in dfll_fetch_common_params()
1570 dev_err(td->dev, "missing clock-output-names property\n"); in dfll_fetch_common_params()
1574 return ok ? 0 : -EINVAL; in dfll_fetch_common_params()
1578 * API exported to per-SoC platform drivers
1582 * tegra_dfll_register - probe a Tegra DFLL device
1584 * @soc: Per-SoC integration and characterization data for this DFLL instance
1587 * by a SoC-specific shim driver that passes in per-SoC integration
1588 * and configuration data via @soc. Returns 0 on success or -err on failure.
1598 dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n"); in tegra_dfll_register()
1599 return -EINVAL; in tegra_dfll_register()
1602 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL); in tegra_dfll_register()
1604 return -ENOMEM; in tegra_dfll_register()
1605 td->dev = &pdev->dev; in tegra_dfll_register()
1608 td->soc = soc; in tegra_dfll_register()
1610 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu"); in tegra_dfll_register()
1611 if (IS_ERR(td->vdd_reg)) { in tegra_dfll_register()
1612 dev_err(td->dev, "couldn't get vdd_cpu regulator\n"); in tegra_dfll_register()
1613 return PTR_ERR(td->vdd_reg); in tegra_dfll_register()
1616 td->dvco_rst = devm_reset_control_get(td->dev, "dvco"); in tegra_dfll_register()
1617 if (IS_ERR(td->dvco_rst)) { in tegra_dfll_register()
1618 dev_err(td->dev, "couldn't get dvco reset\n"); in tegra_dfll_register()
1619 return PTR_ERR(td->dvco_rst); in tegra_dfll_register()
1624 dev_err(td->dev, "couldn't parse device tree parameters\n"); in tegra_dfll_register()
1634 dev_err(td->dev, "no control register resource\n"); in tegra_dfll_register()
1635 return -ENODEV; in tegra_dfll_register()
1638 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
1639 if (!td->base) { in tegra_dfll_register()
1640 dev_err(td->dev, "couldn't ioremap DFLL control registers\n"); in tegra_dfll_register()
1641 return -ENODEV; in tegra_dfll_register()
1646 dev_err(td->dev, "no i2c_base resource\n"); in tegra_dfll_register()
1647 return -ENODEV; in tegra_dfll_register()
1650 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
1651 if (!td->i2c_base) { in tegra_dfll_register()
1652 dev_err(td->dev, "couldn't ioremap i2c_base resource\n"); in tegra_dfll_register()
1653 return -ENODEV; in tegra_dfll_register()
1658 dev_err(td->dev, "no i2c_controller_base resource\n"); in tegra_dfll_register()
1659 return -ENODEV; in tegra_dfll_register()
1662 td->i2c_controller_base = devm_ioremap(td->dev, mem->start, in tegra_dfll_register()
1664 if (!td->i2c_controller_base) { in tegra_dfll_register()
1665 dev_err(td->dev, in tegra_dfll_register()
1667 return -ENODEV; in tegra_dfll_register()
1672 dev_err(td->dev, "no lut_base resource\n"); in tegra_dfll_register()
1673 return -ENODEV; in tegra_dfll_register()
1676 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
1677 if (!td->lut_base) { in tegra_dfll_register()
1678 dev_err(td->dev, in tegra_dfll_register()
1680 return -ENODEV; in tegra_dfll_register()
1685 dev_err(&pdev->dev, "DFLL clock init error\n"); in tegra_dfll_register()
1696 dev_err(&pdev->dev, "DFLL clk registration failed\n"); in tegra_dfll_register()
1707 * tegra_dfll_unregister - release all of the DFLL driver resources for a device
1712 * soc pointer upon success or -EBUSY if the DFLL is still active.
1719 if (td->mode != DFLL_DISABLED) { in tegra_dfll_unregister()
1720 dev_err(&pdev->dev, in tegra_dfll_unregister()
1722 return ERR_PTR(-EBUSY); in tegra_dfll_unregister()
1725 debugfs_remove_recursive(td->debugfs_dir); in tegra_dfll_unregister()
1728 pm_runtime_disable(&pdev->dev); in tegra_dfll_unregister()
1730 clk_unprepare(td->ref_clk); in tegra_dfll_unregister()
1731 clk_unprepare(td->soc_clk); in tegra_dfll_unregister()
1732 clk_unprepare(td->i2c_clk); in tegra_dfll_unregister()
1734 reset_control_assert(td->dvco_rst); in tegra_dfll_unregister()
1736 return td->soc; in tegra_dfll_unregister()