Lines Matching +full:timing +full:-
2 * drivers/clk/tegra/clk-emc.c
19 #include <linux/clk-provider.h>
54 * When we change the timing to a timing with a parent that has the same
56 * timing that has a different clock source.
108 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
123 struct emc_timing *timing = NULL; in emc_determine_rate() local
128 for (i = 0; i < tegra->num_timings; i++) { in emc_determine_rate()
129 if (tegra->timings[i].ram_code != ram_code) in emc_determine_rate()
132 timing = tegra->timings + i; in emc_determine_rate()
134 if (timing->rate > req->max_rate) { in emc_determine_rate()
136 req->rate = tegra->timings[i - 1].rate; in emc_determine_rate()
140 if (timing->rate < req->min_rate) in emc_determine_rate()
143 if (timing->rate >= req->rate) { in emc_determine_rate()
144 req->rate = timing->rate; in emc_determine_rate()
149 if (timing) { in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
154 req->rate = clk_hw_get_rate(hw); in emc_determine_rate()
165 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_get_parent()
175 if (tegra->emc) in emc_ensure_emc_driver()
176 return tegra->emc; in emc_ensure_emc_driver()
178 if (!tegra->emc_node) in emc_ensure_emc_driver()
181 pdev = of_find_device_by_node(tegra->emc_node); in emc_ensure_emc_driver()
188 of_node_put(tegra->emc_node); in emc_ensure_emc_driver()
189 tegra->emc_node = NULL; in emc_ensure_emc_driver()
191 tegra->emc = platform_get_drvdata(pdev); in emc_ensure_emc_driver()
192 if (!tegra->emc) { in emc_ensure_emc_driver()
197 return tegra->emc; in emc_ensure_emc_driver()
201 struct emc_timing *timing) in emc_set_timing() argument
210 return -ENOENT; in emc_set_timing()
212 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate, in emc_set_timing()
213 timing->parent_rate, __clk_get_name(timing->parent)); in emc_set_timing()
215 if (emc_get_parent(&tegra->hw) == timing->parent_index && in emc_set_timing()
216 clk_get_rate(timing->parent) != timing->parent_rate) { in emc_set_timing()
218 return -EINVAL; in emc_set_timing()
221 tegra->changing_timing = true; in emc_set_timing()
223 err = clk_set_rate(timing->parent, timing->parent_rate); in emc_set_timing()
226 __clk_get_name(timing->parent), timing->parent_rate, in emc_set_timing()
232 err = clk_prepare_enable(timing->parent); in emc_set_timing()
238 div = timing->parent_rate / (timing->rate / 2) - 2; in emc_set_timing()
240 err = tegra_emc_prepare_timing_change(emc, timing->rate); in emc_set_timing()
244 spin_lock_irqsave(tegra->lock, flags); in emc_set_timing()
246 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
249 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index); in emc_set_timing()
254 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
256 spin_unlock_irqrestore(tegra->lock, flags); in emc_set_timing()
258 tegra_emc_complete_timing_change(emc, timing->rate); in emc_set_timing()
260 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); in emc_set_timing()
261 clk_disable_unprepare(tegra->prev_parent); in emc_set_timing()
263 tegra->prev_parent = timing->parent; in emc_set_timing()
264 tegra->changing_timing = false; in emc_set_timing()
270 * Get backup timing to use as an intermediate step when a change between
272 * find a timing with a higher clock rate to avoid a rate below any set rate
280 struct emc_timing *timing; in get_backup_timing() local
282 for (i = timing_index+1; i < tegra->num_timings; i++) { in get_backup_timing()
283 timing = tegra->timings + i; in get_backup_timing()
284 if (timing->ram_code != ram_code) in get_backup_timing()
287 if (emc_parent_clk_sources[timing->parent_index] != in get_backup_timing()
289 tegra->timings[timing_index].parent_index]) in get_backup_timing()
290 return timing; in get_backup_timing()
293 for (i = timing_index-1; i >= 0; --i) { in get_backup_timing()
294 timing = tegra->timings + i; in get_backup_timing()
295 if (timing->ram_code != ram_code) in get_backup_timing()
298 if (emc_parent_clk_sources[timing->parent_index] != in get_backup_timing()
300 tegra->timings[timing_index].parent_index]) in get_backup_timing()
301 return timing; in get_backup_timing()
311 struct emc_timing *timing = NULL; in emc_set_rate() local
325 if (tegra->changing_timing) in emc_set_rate()
328 for (i = 0; i < tegra->num_timings; i++) { in emc_set_rate()
329 if (tegra->timings[i].rate == rate && in emc_set_rate()
330 tegra->timings[i].ram_code == ram_code) { in emc_set_rate()
331 timing = tegra->timings + i; in emc_set_rate()
336 if (!timing) { in emc_set_rate()
338 return -EINVAL; in emc_set_rate()
342 emc_parent_clk_sources[timing->parent_index] && in emc_set_rate()
343 clk_get_rate(timing->parent) != timing->parent_rate) { in emc_set_rate()
353 pr_err("cannot find backup timing\n"); in emc_set_rate()
354 return -EINVAL; in emc_set_rate()
358 backup_timing->rate, rate); in emc_set_rate()
362 pr_err("cannot set backup timing: %d\n", err); in emc_set_rate()
367 return emc_set_timing(tegra, timing); in emc_set_rate()
373 struct emc_timing *timing, in load_one_timing_from_dt() argument
379 err = of_property_read_u32(node, "clock-frequency", &tmp); in load_one_timing_from_dt()
381 pr_err("timing %pOF: failed to read rate\n", node); in load_one_timing_from_dt()
385 timing->rate = tmp; in load_one_timing_from_dt()
387 err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp); in load_one_timing_from_dt()
389 pr_err("timing %pOF: failed to read parent rate\n", node); in load_one_timing_from_dt()
393 timing->parent_rate = tmp; in load_one_timing_from_dt()
395 timing->parent = of_clk_get_by_name(node, "emc-parent"); in load_one_timing_from_dt()
396 if (IS_ERR(timing->parent)) { in load_one_timing_from_dt()
397 pr_err("timing %pOF: failed to get parent clock\n", node); in load_one_timing_from_dt()
398 return PTR_ERR(timing->parent); in load_one_timing_from_dt()
401 timing->parent_index = 0xff; in load_one_timing_from_dt()
404 __clk_get_name(timing->parent))) { in load_one_timing_from_dt()
405 timing->parent_index = i; in load_one_timing_from_dt()
409 if (timing->parent_index == 0xff) { in load_one_timing_from_dt()
410 pr_err("timing %pOF: %s is not a valid parent\n", in load_one_timing_from_dt()
411 node, __clk_get_name(timing->parent)); in load_one_timing_from_dt()
412 clk_put(timing->parent); in load_one_timing_from_dt()
413 return -EINVAL; in load_one_timing_from_dt()
424 if (a->rate < b->rate) in cmp_timings()
425 return -1; in cmp_timings()
426 else if (a->rate == b->rate) in cmp_timings()
440 tegra->timings = kcalloc(child_count, sizeof(struct emc_timing), in load_timings_from_dt()
442 if (!tegra->timings) in load_timings_from_dt()
443 return -ENOMEM; in load_timings_from_dt()
445 tegra->num_timings = child_count; in load_timings_from_dt()
448 struct emc_timing *timing = tegra->timings + (i++); in load_timings_from_dt() local
450 err = load_one_timing_from_dt(tegra, timing, child); in load_timings_from_dt()
456 timing->ram_code = ram_code; in load_timings_from_dt()
459 sort(tegra->timings, tegra->num_timings, sizeof(struct emc_timing), in load_timings_from_dt()
484 return ERR_PTR(-ENOMEM); in tegra_clk_register_emc()
486 tegra->clk_regs = base; in tegra_clk_register_emc()
487 tegra->lock = lock; in tegra_clk_register_emc()
489 tegra->num_timings = 0; in tegra_clk_register_emc()
492 err = of_property_read_u32(node, "nvidia,ram-code", in tegra_clk_register_emc()
508 if (tegra->num_timings == 0) in tegra_clk_register_emc()
511 tegra->emc_node = of_parse_phandle(np, in tegra_clk_register_emc()
512 "nvidia,external-memory-controller", 0); in tegra_clk_register_emc()
513 if (!tegra->emc_node) in tegra_clk_register_emc()
522 tegra->hw.init = &init; in tegra_clk_register_emc()
524 clk = clk_register(NULL, &tegra->hw); in tegra_clk_register_emc()
528 tegra->prev_parent = clk_hw_get_parent_by_index( in tegra_clk_register_emc()
529 &tegra->hw, emc_get_parent(&tegra->hw))->clk; in tegra_clk_register_emc()
530 tegra->changing_timing = false; in tegra_clk_register_emc()
533 clk_register_clkdev(clk, "emc", "tegra-clk-debug"); in tegra_clk_register_emc()