22 #include <linux/clk-provider.h>
39 #define super_state_to_src_shift(m, s) ((m->width * s))
40 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
44 	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);  in clk_super_get_parent()  local
48 	val = readl_relaxed(mux->reg);  in clk_super_get_parent()
55 		super_state_to_src_shift(mux, SUPER_STATE_IDLE) :  in clk_super_get_parent()
56 		super_state_to_src_shift(mux, SUPER_STATE_RUN);  in clk_super_get_parent()
58 	source = (val >> shift) & super_state_to_src_mask(mux);  in clk_super_get_parent()
64 	if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&  in clk_super_get_parent()
65 	    (source == mux->pllx_index))  in clk_super_get_parent()
66 		source = mux->div2_index;  in clk_super_get_parent()
73 	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);  in clk_super_set_parent()  local
79 	if (mux->lock)  in clk_super_set_parent()
80 		spin_lock_irqsave(mux->lock, flags);  in clk_super_set_parent()
82 	val = readl_relaxed(mux->reg);  in clk_super_set_parent()
87 		super_state_to_src_shift(mux, SUPER_STATE_IDLE) :  in clk_super_set_parent()
88 		super_state_to_src_shift(mux, SUPER_STATE_RUN);  in clk_super_set_parent()
91 	 * For LP mode super-clock switch between PLLX direct  in clk_super_set_parent()
92 	 * and divided-by-2 outputs is allowed only when other  in clk_super_set_parent()
95 	if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||  in clk_super_set_parent()
96 					       (index == mux->pllx_index))) {  in clk_super_set_parent()
98 		if ((parent_index == mux->div2_index) ||  in clk_super_set_parent()
99 		    (parent_index == mux->pllx_index)) {  in clk_super_set_parent()
100 			err = -EINVAL;  in clk_super_set_parent()
105 		writel_relaxed(val, mux->reg);  in clk_super_set_parent()
108 		if (index == mux->div2_index)  in clk_super_set_parent()
109 			index = mux->pllx_index;  in clk_super_set_parent()
111 	val &= ~((super_state_to_src_mask(mux)) << shift);  in clk_super_set_parent()
112 	val |= (index & (super_state_to_src_mask(mux))) << shift;  in clk_super_set_parent()
114 	writel_relaxed(val, mux->reg);  in clk_super_set_parent()
118 	if (mux->lock)  in clk_super_set_parent()
119 		spin_unlock_irqrestore(mux->lock, flags);  in clk_super_set_parent()
133 	struct clk_hw *div_hw = &super->frac_div.hw;  in clk_super_round_rate()
137 	return super->div_ops->round_rate(div_hw, rate, parent_rate);  in clk_super_round_rate()
144 	struct clk_hw *div_hw = &super->frac_div.hw;  in clk_super_recalc_rate()
148 	return super->div_ops->recalc_rate(div_hw, parent_rate);  in clk_super_recalc_rate()
155 	struct clk_hw *div_hw = &super->frac_div.hw;  in clk_super_set_rate()
159 	return super->div_ops->set_rate(div_hw, rate, parent_rate);  in clk_super_set_rate()
172 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,  in tegra_clk_register_super_mux()  argument
181 		return ERR_PTR(-ENOMEM);  in tegra_clk_register_super_mux()
189 	super->reg = reg;  in tegra_clk_register_super_mux()
190 	super->pllx_index = pllx_index;  in tegra_clk_register_super_mux()
191 	super->div2_index = div2_index;  in tegra_clk_register_super_mux()
192 	super->lock = lock;  in tegra_clk_register_super_mux()
193 	super->width = width;  in tegra_clk_register_super_mux()
194 	super->flags = clk_super_flags;  in tegra_clk_register_super_mux()
197 	super->hw.init = &init;  in tegra_clk_register_super_mux()
199 	clk = clk_register(NULL, &super->hw);  in tegra_clk_register_super_mux()
208 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,  in tegra_clk_register_super_clk()  argument
217 		return ERR_PTR(-ENOMEM);  in tegra_clk_register_super_clk()
225 	super->reg = reg;  in tegra_clk_register_super_clk()
226 	super->lock = lock;  in tegra_clk_register_super_clk()
227 	super->width = 4;  in tegra_clk_register_super_clk()
228 	super->flags = clk_super_flags;  in tegra_clk_register_super_clk()
229 	super->frac_div.reg = reg + 4;  in tegra_clk_register_super_clk()
230 	super->frac_div.shift = 16;  in tegra_clk_register_super_clk()
231 	super->frac_div.width = 8;  in tegra_clk_register_super_clk()
232 	super->frac_div.frac_width = 1;  in tegra_clk_register_super_clk()
233 	super->frac_div.lock = lock;  in tegra_clk_register_super_clk()
234 	super->div_ops = &tegra_clk_frac_div_ops;  in tegra_clk_register_super_clk()
237 	super->hw.init = &init;  in tegra_clk_register_super_clk()
239 	clk = clk_register(NULL, &super->hw);  in tegra_clk_register_super_clk()