Lines Matching +full:tegra210 +full:- +full:emc
18 #include <linux/clk-provider.h>
27 #include "clk-id.h"
144 #define MASK(x) (BIT(x) - 1)
803 * Critical for RAM re-repair operation, which must occur on resume
813 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
826 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
899 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
903 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
907 data->periph.gate.regs = bank; in periph_clk_init()
925 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in gate_clk_init()
929 clk = tegra_clk_register_periph_gate(data->name, in gate_clk_init()
930 data->p.parent_name, data->periph.gate.flags, in gate_clk_init()
931 clk_base, data->flags, in gate_clk_init()
932 data->periph.gate.clk_num, in gate_clk_init()
950 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in div_clk_init()
954 clk = tegra_clk_register_divider(data->name, in div_clk_init()
955 data->p.parent_name, clk_base + data->offset, in div_clk_init()
956 data->flags, data->periph.divider.flags, in div_clk_init()
957 data->periph.divider.shift, in div_clk_init()
958 data->periph.divider.width, in div_clk_init()
959 data->periph.divider.frac_width, in div_clk_init()
960 data->periph.divider.lock); in div_clk_init()
987 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in init_pllp()
991 clk = tegra_clk_register_divider(data->div_name, "pll_p", in init_pllp()
992 clk_base + data->offset, 0, data->div_flags, in init_pllp()
993 data->div_shift, 8, 1, data->lock); in init_pllp()
994 clk = tegra_clk_register_pll_out(data->pll_out_name, in init_pllp()
995 data->div_name, clk_base + data->offset, in init_pllp()
996 data->rst_shift + 1, data->rst_shift, in init_pllp()
998 data->lock); in init_pllp()
1006 * Tegra210 has control on enabling/disabling PLLP branches to in init_pllp()
1009 * re-parenting CPU off from "pll_p_out4" the PLLP branching to in init_pllp()