Lines Matching +full:0 +full:x2ac

29 #define CLK_OUT_ENB_L			0x010
30 #define CLK_OUT_ENB_H			0x014
31 #define CLK_OUT_ENB_U			0x018
32 #define CLK_OUT_ENB_V			0x360
33 #define CLK_OUT_ENB_W			0x364
34 #define CLK_OUT_ENB_X			0x280
35 #define CLK_OUT_ENB_Y			0x298
36 #define CLK_OUT_ENB_SET_L		0x320
37 #define CLK_OUT_ENB_CLR_L		0x324
38 #define CLK_OUT_ENB_SET_H		0x328
39 #define CLK_OUT_ENB_CLR_H		0x32c
40 #define CLK_OUT_ENB_SET_U		0x330
41 #define CLK_OUT_ENB_CLR_U		0x334
42 #define CLK_OUT_ENB_SET_V		0x440
43 #define CLK_OUT_ENB_CLR_V		0x444
44 #define CLK_OUT_ENB_SET_W		0x448
45 #define CLK_OUT_ENB_CLR_W		0x44c
46 #define CLK_OUT_ENB_SET_X		0x284
47 #define CLK_OUT_ENB_CLR_X		0x288
48 #define CLK_OUT_ENB_SET_Y		0x29c
49 #define CLK_OUT_ENB_CLR_Y		0x2a0
51 #define RST_DEVICES_L			0x004
52 #define RST_DEVICES_H			0x008
53 #define RST_DEVICES_U			0x00C
54 #define RST_DEVICES_V			0x358
55 #define RST_DEVICES_W			0x35C
56 #define RST_DEVICES_X			0x28C
57 #define RST_DEVICES_Y			0x2a4
58 #define RST_DEVICES_SET_L		0x300
59 #define RST_DEVICES_CLR_L		0x304
60 #define RST_DEVICES_SET_H		0x308
61 #define RST_DEVICES_CLR_H		0x30c
62 #define RST_DEVICES_SET_U		0x310
63 #define RST_DEVICES_CLR_U		0x314
64 #define RST_DEVICES_SET_V		0x430
65 #define RST_DEVICES_CLR_V		0x434
66 #define RST_DEVICES_SET_W		0x438
67 #define RST_DEVICES_CLR_W		0x43c
68 #define RST_DEVICES_SET_X		0x290
69 #define RST_DEVICES_CLR_X		0x294
70 #define RST_DEVICES_SET_Y		0x2a8
71 #define RST_DEVICES_CLR_Y		0x2ac
89 	[0] = {
164 		return 0;  in tegra_clk_rst_assert()
178 		return 0;  in tegra_clk_rst_deassert()
307 	for (i = 0; i < clk_num; i++) {  in tegra_add_of_provider()
339 	for (i = 0; i < num; i++, dev_clks++)  in tegra_register_devclks()
343 	for (i = 0; i < clk_num; i++) {  in tegra_register_devclks()
364 		return 0;  in tegra_clocks_apply_init_table()
368 	return 0;  in tegra_clocks_apply_init_table()