88 	 * bits of the v PLL divider. Bit 8 is tied low and always zero,  in vco_get()
95 		vco->v = val & INTEGRATOR_AP_CM_BITS;  in vco_get()
103 	 * access the low eight bits of the v PLL divider. Bit 8 is tied low  in vco_get()
110 		vco->v = val & INTEGRATOR_AP_SYS_BITS;  in vco_get()
120 	 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the  in vco_get()
121 	 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies  in vco_get()
122 	 * 33 or 25 MHz respectively.  in vco_get()
127 		vco->v = divxy ? 17 : 14;  in vco_get()
135 	 * of the v PLL divider. Bit 8 is tied low and always zero,  in vco_get()
142 		vco->v = val & 0xFF;  in vco_get()
149 		vco->v = (val >> 12) & 0xFF;  in vco_get()
155 	vco->v = val & 0x1ff;  in vco_get()
176 		val = vco.v & 0xFF;  in vco_set()
177 		if (vco.v & 0x100)  in vco_set()
186 		val = vco.v & 0xFF;  in vco_set()
187 		if (vco.v & 0x100)  in vco_set()
196 		val = (vco.v & 0xFF) | vco.s << 8;  in vco_set()
197 		if (vco.v & 0x100)  in vco_set()
204 		val = ((vco.v & 0xFF) << 12) | (vco.s << 20);  in vco_set()
205 		if (vco.v & 0x100)  in vco_set()
213 		val = vco.v | (vco.r << 9) | (vco.s << 16);  in vco_set()
288 		 * If we're below or less than halfway from 25 to 33 MHz  in icst_round_rate()
289 		 * select 25 MHz  in icst_round_rate()
484 	/* Minimum 25 MHz */
485 	.vd_min		= 25,