Lines Matching +full:multi +full:- +full:system

142 	  Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
163 	  Support for Multi Timer Unit. MTU provides access
165 	  32-bit free running decrementing counters.
171 	  Use the Multi Timer Unit as the sched_clock.
225 	bool "Integrator-ap timer driver" if COMPILE_TEST
228 	  Enables support for the Integrator-ap timer.
268 	  available on many OMAP-like platforms.
293 	bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
297 	  These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
302 	bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
306 	  This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP)
324 	  power-of-2 divisor of the clock rate. The behaviour can also be
327 	  The main use of the event stream is wfe-based timeouts of userspace
338 	bool "Workaround for Freescale/NXP Erratum A-008585"
344 	  A-008585 ("ARM generic timer may contain an erroneous
346 	  fsl,erratum-a008585 property is found in the timer node.
355 	  161010101. The workaround will be active if the hisilicon,erratum-161010101
359 	bool "Workaround for Cortex-A73 erratum 858921"
364 	  This option enables a workaround applicable to Cortex-A73
377 	  allwinner,erratum-unknown1 property is found in the timer node.
400 	bool "Support for the ARMv7M system time" if COMPILE_TEST
404 	  This options enables support for the ARMv7M system timer unit
419 	bool "Exynos multi core timer driver" if COMPILE_TEST
422 	  Support for Multi Core Timer controller on Exynos SoCs.
483 	bool "J-Core PIT timer driver" if COMPILE_TEST
489 	  the integrated PIT in the J-Core synthesizable, open source SoC.
497 	  the Compare Match Timer (CMT) hardware available in 16/32/48-bit
505 	  This enables build of a clockevent driver for the Multi-Function
507 	  This hardware comes with 16 bit-timer registers.
521 	  the 32-bit Timer Unit (TMU) hardware available on a wide range
530 	  the 48-bit System Timer (STI) hardware available on a SoCs
548 	  counter available in the "System Registers" block of
566 	bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST
570 	  This enables OST0 support available on PXA and SA-11x0
625 	bool "Timer for the RISC-V platform"
631 	  This enables the per-hart timer built into all RISC-V systems, which
633 	  required for all RISC-V systems.