2  * SuperH Timer Support - MTU2
59 #define TSTR -1 /* shared register */
64 #define TSR  4 /* channel register */
79 /* Values 4 to 7 are channel-dependent */
84 #define TCR_TPSC_CH0_TCLKA	(4 << 0)
88 #define TCR_TPSC_CH1_TCLKA	(4 << 0)
92 #define TCR_TPSC_CH2_TCLKA	(4 << 0)
96 #define TCR_TPSC_CH34_P256	(4 << 0)
104 #define TMDR_BFA		(1 << 4)
108 #define TMDR_MD_PHASE_1		(4 << 0)
118 #define TIOC_IOCH(n)		((n) << 4)
136 #define TIER_TCIEV		(1 << 4)
144 #define TSR_TCFV		(1 << 4)
154 	[TIER] = 4,
160 static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)  in sh_mtu2_read()  argument
165 		return ioread8(ch->mtu->mapbase + 0x280);  in sh_mtu2_read()
170 		return ioread16(ch->base + offs);  in sh_mtu2_read()
172 		return ioread8(ch->base + offs);  in sh_mtu2_read()
175 static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,  in sh_mtu2_write()  argument
181 		return iowrite8(value, ch->mtu->mapbase + 0x280);  in sh_mtu2_write()
186 		iowrite16(value, ch->base + offs);  in sh_mtu2_write()
188 		iowrite8(value, ch->base + offs);  in sh_mtu2_write()
191 static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)  in sh_mtu2_start_stop_ch()  argument
196 	raw_spin_lock_irqsave(&ch->mtu->lock, flags);  in sh_mtu2_start_stop_ch()
197 	value = sh_mtu2_read(ch, TSTR);  in sh_mtu2_start_stop_ch()
200 		value |= 1 << ch->index;  in sh_mtu2_start_stop_ch()
202 		value &= ~(1 << ch->index);  in sh_mtu2_start_stop_ch()
204 	sh_mtu2_write(ch, TSTR, value);  in sh_mtu2_start_stop_ch()
205 	raw_spin_unlock_irqrestore(&ch->mtu->lock, flags);  in sh_mtu2_start_stop_ch()
208 static int sh_mtu2_enable(struct sh_mtu2_channel *ch)  in sh_mtu2_enable()  argument
214 	pm_runtime_get_sync(&ch->mtu->pdev->dev);  in sh_mtu2_enable()
215 	dev_pm_syscore_device(&ch->mtu->pdev->dev, true);  in sh_mtu2_enable()
218 	ret = clk_enable(ch->mtu->clk);  in sh_mtu2_enable()
220 		dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",  in sh_mtu2_enable()
221 			ch->index);  in sh_mtu2_enable()
226 	sh_mtu2_start_stop_ch(ch, 0);  in sh_mtu2_enable()
228 	rate = clk_get_rate(ch->mtu->clk) / 64;  in sh_mtu2_enable()
235 	sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);  in sh_mtu2_enable()
236 	sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |  in sh_mtu2_enable()
238 	sh_mtu2_write(ch, TGR, periodic);  in sh_mtu2_enable()
239 	sh_mtu2_write(ch, TCNT, 0);  in sh_mtu2_enable()
240 	sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);  in sh_mtu2_enable()
241 	sh_mtu2_write(ch, TIER, TIER_TGIEA);  in sh_mtu2_enable()
244 	sh_mtu2_start_stop_ch(ch, 1);  in sh_mtu2_enable()
249 static void sh_mtu2_disable(struct sh_mtu2_channel *ch)  in sh_mtu2_disable()  argument
252 	sh_mtu2_start_stop_ch(ch, 0);  in sh_mtu2_disable()
255 	clk_disable(ch->mtu->clk);  in sh_mtu2_disable()
257 	dev_pm_syscore_device(&ch->mtu->pdev->dev, false);  in sh_mtu2_disable()
258 	pm_runtime_put(&ch->mtu->pdev->dev);  in sh_mtu2_disable()
263 	struct sh_mtu2_channel *ch = dev_id;  in sh_mtu2_interrupt()  local
266 	sh_mtu2_read(ch, TSR);  in sh_mtu2_interrupt()
267 	sh_mtu2_write(ch, TSR, ~TSR_TGFA);  in sh_mtu2_interrupt()
270 	ch->ced.event_handler(&ch->ced);  in sh_mtu2_interrupt()
281 	struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);  in sh_mtu2_clock_event_shutdown()  local
284 		sh_mtu2_disable(ch);  in sh_mtu2_clock_event_shutdown()
291 	struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);  in sh_mtu2_clock_event_set_periodic()  local
294 		sh_mtu2_disable(ch);  in sh_mtu2_clock_event_set_periodic()
296 	dev_info(&ch->mtu->pdev->dev, "ch%u: used for periodic clock events\n",  in sh_mtu2_clock_event_set_periodic()
297 		 ch->index);  in sh_mtu2_clock_event_set_periodic()
298 	sh_mtu2_enable(ch);  in sh_mtu2_clock_event_set_periodic()
304 	pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);  in sh_mtu2_clock_event_suspend()
309 	pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);  in sh_mtu2_clock_event_resume()
312 static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,  in sh_mtu2_register_clockevent()  argument
315 	struct clock_event_device *ced = &ch->ced;  in sh_mtu2_register_clockevent()
317 	ced->name = name;  in sh_mtu2_register_clockevent()
318 	ced->features = CLOCK_EVT_FEAT_PERIODIC;  in sh_mtu2_register_clockevent()
319 	ced->rating = 200;  in sh_mtu2_register_clockevent()
320 	ced->cpumask = cpu_possible_mask;  in sh_mtu2_register_clockevent()
321 	ced->set_state_shutdown = sh_mtu2_clock_event_shutdown;  in sh_mtu2_register_clockevent()
322 	ced->set_state_periodic = sh_mtu2_clock_event_set_periodic;  in sh_mtu2_register_clockevent()
323 	ced->suspend = sh_mtu2_clock_event_suspend;  in sh_mtu2_register_clockevent()
324 	ced->resume = sh_mtu2_clock_event_resume;  in sh_mtu2_register_clockevent()
326 	dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",  in sh_mtu2_register_clockevent()
327 		 ch->index);  in sh_mtu2_register_clockevent()
331 static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name)  in sh_mtu2_register()  argument
333 	ch->mtu->has_clockevent = true;  in sh_mtu2_register()
334 	sh_mtu2_register_clockevent(ch, name);  in sh_mtu2_register()
339 static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,  in sh_mtu2_setup_channel()  argument
349 	ch->mtu = mtu;  in sh_mtu2_setup_channel()
352 	irq = platform_get_irq_byname(mtu->pdev, name);  in sh_mtu2_setup_channel()
360 			  dev_name(&ch->mtu->pdev->dev), ch);  in sh_mtu2_setup_channel()
362 		dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",  in sh_mtu2_setup_channel()
367 	ch->base = mtu->mapbase + channel_offsets[index];  in sh_mtu2_setup_channel()
368 	ch->index = index;  in sh_mtu2_setup_channel()
370 	return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev));  in sh_mtu2_setup_channel()
377 	res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0);  in sh_mtu2_map_memory()
379 		dev_err(&mtu->pdev->dev, "failed to get I/O memory\n");  in sh_mtu2_map_memory()
380 		return -ENXIO;  in sh_mtu2_map_memory()
383 	mtu->mapbase = ioremap_nocache(res->start, resource_size(res));  in sh_mtu2_map_memory()
384 	if (mtu->mapbase == NULL)  in sh_mtu2_map_memory()
385 		return -ENXIO;  in sh_mtu2_map_memory()
396 	mtu->pdev = pdev;  in sh_mtu2_setup()
398 	raw_spin_lock_init(&mtu->lock);  in sh_mtu2_setup()
401 	mtu->clk = clk_get(&mtu->pdev->dev, "fck");  in sh_mtu2_setup()
402 	if (IS_ERR(mtu->clk)) {  in sh_mtu2_setup()
403 		dev_err(&mtu->pdev->dev, "cannot get clock\n");  in sh_mtu2_setup()
404 		return PTR_ERR(mtu->clk);  in sh_mtu2_setup()
407 	ret = clk_prepare(mtu->clk);  in sh_mtu2_setup()
414 		dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n");  in sh_mtu2_setup()
419 	mtu->num_channels = 3;  in sh_mtu2_setup()
421 	mtu->channels = kcalloc(mtu->num_channels, sizeof(*mtu->channels),  in sh_mtu2_setup()
423 	if (mtu->channels == NULL) {  in sh_mtu2_setup()
424 		ret = -ENOMEM;  in sh_mtu2_setup()
428 	for (i = 0; i < mtu->num_channels; ++i) {  in sh_mtu2_setup()
429 		ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);  in sh_mtu2_setup()
439 	kfree(mtu->channels);  in sh_mtu2_setup()
440 	iounmap(mtu->mapbase);  in sh_mtu2_setup()
442 	clk_unprepare(mtu->clk);  in sh_mtu2_setup()
444 	clk_put(mtu->clk);  in sh_mtu2_setup()
454 		pm_runtime_set_active(&pdev->dev);  in sh_mtu2_probe()
455 		pm_runtime_enable(&pdev->dev);  in sh_mtu2_probe()
459 		dev_info(&pdev->dev, "kept as earlytimer\n");  in sh_mtu2_probe()
465 		return -ENOMEM;  in sh_mtu2_probe()
470 		pm_runtime_idle(&pdev->dev);  in sh_mtu2_probe()
477 	if (mtu->has_clockevent)  in sh_mtu2_probe()
478 		pm_runtime_irq_safe(&pdev->dev);  in sh_mtu2_probe()
480 		pm_runtime_idle(&pdev->dev);  in sh_mtu2_probe()
487 	return -EBUSY; /* cannot unregister clockevent */  in sh_mtu2_remove()
491 	{ "sh-mtu2", 0 },