Lines Matching +full:4 +full:- +full:ch
2 * SuperH Timer Support - TMU
74 #define TSTR -1 /* shared register */
85 #define TCR_TPSC_CLK1024 (4 << 0)
88 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) in sh_tmu_read() argument
93 switch (ch->tmu->model) { in sh_tmu_read()
95 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
97 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
104 return ioread16(ch->base + offs); in sh_tmu_read()
106 return ioread32(ch->base + offs); in sh_tmu_read()
109 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, in sh_tmu_write() argument
115 switch (ch->tmu->model) { in sh_tmu_write()
117 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
119 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
126 iowrite16(value, ch->base + offs); in sh_tmu_write()
128 iowrite32(value, ch->base + offs); in sh_tmu_write()
131 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) in sh_tmu_start_stop_ch() argument
136 raw_spin_lock_irqsave(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
137 value = sh_tmu_read(ch, TSTR); in sh_tmu_start_stop_ch()
140 value |= 1 << ch->index; in sh_tmu_start_stop_ch()
142 value &= ~(1 << ch->index); in sh_tmu_start_stop_ch()
144 sh_tmu_write(ch, TSTR, value); in sh_tmu_start_stop_ch()
145 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
148 static int __sh_tmu_enable(struct sh_tmu_channel *ch) in __sh_tmu_enable() argument
153 ret = clk_enable(ch->tmu->clk); in __sh_tmu_enable()
155 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", in __sh_tmu_enable()
156 ch->index); in __sh_tmu_enable()
161 sh_tmu_start_stop_ch(ch, 0); in __sh_tmu_enable()
164 sh_tmu_write(ch, TCOR, 0xffffffff); in __sh_tmu_enable()
165 sh_tmu_write(ch, TCNT, 0xffffffff); in __sh_tmu_enable()
167 /* configure channel to parent clock / 4, irq off */ in __sh_tmu_enable()
168 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_enable()
171 sh_tmu_start_stop_ch(ch, 1); in __sh_tmu_enable()
176 static int sh_tmu_enable(struct sh_tmu_channel *ch) in sh_tmu_enable() argument
178 if (ch->enable_count++ > 0) in sh_tmu_enable()
181 pm_runtime_get_sync(&ch->tmu->pdev->dev); in sh_tmu_enable()
182 dev_pm_syscore_device(&ch->tmu->pdev->dev, true); in sh_tmu_enable()
184 return __sh_tmu_enable(ch); in sh_tmu_enable()
187 static void __sh_tmu_disable(struct sh_tmu_channel *ch) in __sh_tmu_disable() argument
190 sh_tmu_start_stop_ch(ch, 0); in __sh_tmu_disable()
193 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_disable()
196 clk_disable(ch->tmu->clk); in __sh_tmu_disable()
199 static void sh_tmu_disable(struct sh_tmu_channel *ch) in sh_tmu_disable() argument
201 if (WARN_ON(ch->enable_count == 0)) in sh_tmu_disable()
204 if (--ch->enable_count > 0) in sh_tmu_disable()
207 __sh_tmu_disable(ch); in sh_tmu_disable()
209 dev_pm_syscore_device(&ch->tmu->pdev->dev, false); in sh_tmu_disable()
210 pm_runtime_put(&ch->tmu->pdev->dev); in sh_tmu_disable()
213 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, in sh_tmu_set_next() argument
217 sh_tmu_start_stop_ch(ch, 0); in sh_tmu_set_next()
220 sh_tmu_read(ch, TCR); in sh_tmu_set_next()
223 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_set_next()
227 sh_tmu_write(ch, TCOR, delta); in sh_tmu_set_next()
229 sh_tmu_write(ch, TCOR, 0xffffffff); in sh_tmu_set_next()
231 sh_tmu_write(ch, TCNT, delta); in sh_tmu_set_next()
234 sh_tmu_start_stop_ch(ch, 1); in sh_tmu_set_next()
239 struct sh_tmu_channel *ch = dev_id; in sh_tmu_interrupt() local
242 if (clockevent_state_oneshot(&ch->ced)) in sh_tmu_interrupt()
243 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in sh_tmu_interrupt()
245 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_interrupt()
248 ch->ced.event_handler(&ch->ced); in sh_tmu_interrupt()
259 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_read() local
261 return sh_tmu_read(ch, TCNT) ^ 0xffffffff; in sh_tmu_clocksource_read()
266 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_enable() local
269 if (WARN_ON(ch->cs_enabled)) in sh_tmu_clocksource_enable()
272 ret = sh_tmu_enable(ch); in sh_tmu_clocksource_enable()
274 ch->cs_enabled = true; in sh_tmu_clocksource_enable()
281 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_disable() local
283 if (WARN_ON(!ch->cs_enabled)) in sh_tmu_clocksource_disable()
286 sh_tmu_disable(ch); in sh_tmu_clocksource_disable()
287 ch->cs_enabled = false; in sh_tmu_clocksource_disable()
292 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_suspend() local
294 if (!ch->cs_enabled) in sh_tmu_clocksource_suspend()
297 if (--ch->enable_count == 0) { in sh_tmu_clocksource_suspend()
298 __sh_tmu_disable(ch); in sh_tmu_clocksource_suspend()
299 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev); in sh_tmu_clocksource_suspend()
305 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_resume() local
307 if (!ch->cs_enabled) in sh_tmu_clocksource_resume()
310 if (ch->enable_count++ == 0) { in sh_tmu_clocksource_resume()
311 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev); in sh_tmu_clocksource_resume()
312 __sh_tmu_enable(ch); in sh_tmu_clocksource_resume()
316 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, in sh_tmu_register_clocksource() argument
319 struct clocksource *cs = &ch->cs; in sh_tmu_register_clocksource()
321 cs->name = name; in sh_tmu_register_clocksource()
322 cs->rating = 200; in sh_tmu_register_clocksource()
323 cs->read = sh_tmu_clocksource_read; in sh_tmu_register_clocksource()
324 cs->enable = sh_tmu_clocksource_enable; in sh_tmu_register_clocksource()
325 cs->disable = sh_tmu_clocksource_disable; in sh_tmu_register_clocksource()
326 cs->suspend = sh_tmu_clocksource_suspend; in sh_tmu_register_clocksource()
327 cs->resume = sh_tmu_clocksource_resume; in sh_tmu_register_clocksource()
328 cs->mask = CLOCKSOURCE_MASK(32); in sh_tmu_register_clocksource()
329 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; in sh_tmu_register_clocksource()
331 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", in sh_tmu_register_clocksource()
332 ch->index); in sh_tmu_register_clocksource()
334 clocksource_register_hz(cs, ch->tmu->rate); in sh_tmu_register_clocksource()
343 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) in sh_tmu_clock_event_start() argument
345 sh_tmu_enable(ch); in sh_tmu_clock_event_start()
348 ch->periodic = (ch->tmu->rate + HZ/2) / HZ; in sh_tmu_clock_event_start()
349 sh_tmu_set_next(ch, ch->periodic, 1); in sh_tmu_clock_event_start()
355 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); in sh_tmu_clock_event_shutdown() local
358 sh_tmu_disable(ch); in sh_tmu_clock_event_shutdown()
365 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); in sh_tmu_clock_event_set_state() local
369 sh_tmu_disable(ch); in sh_tmu_clock_event_set_state()
371 dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n", in sh_tmu_clock_event_set_state()
372 ch->index, periodic ? "periodic" : "oneshot"); in sh_tmu_clock_event_set_state()
373 sh_tmu_clock_event_start(ch, periodic); in sh_tmu_clock_event_set_state()
390 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); in sh_tmu_clock_event_next() local
395 sh_tmu_set_next(ch, delta, 0); in sh_tmu_clock_event_next()
401 pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev); in sh_tmu_clock_event_suspend()
406 pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev); in sh_tmu_clock_event_resume()
409 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, in sh_tmu_register_clockevent() argument
412 struct clock_event_device *ced = &ch->ced; in sh_tmu_register_clockevent()
415 ced->name = name; in sh_tmu_register_clockevent()
416 ced->features = CLOCK_EVT_FEAT_PERIODIC; in sh_tmu_register_clockevent()
417 ced->features |= CLOCK_EVT_FEAT_ONESHOT; in sh_tmu_register_clockevent()
418 ced->rating = 200; in sh_tmu_register_clockevent()
419 ced->cpumask = cpu_possible_mask; in sh_tmu_register_clockevent()
420 ced->set_next_event = sh_tmu_clock_event_next; in sh_tmu_register_clockevent()
421 ced->set_state_shutdown = sh_tmu_clock_event_shutdown; in sh_tmu_register_clockevent()
422 ced->set_state_periodic = sh_tmu_clock_event_set_periodic; in sh_tmu_register_clockevent()
423 ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; in sh_tmu_register_clockevent()
424 ced->suspend = sh_tmu_clock_event_suspend; in sh_tmu_register_clockevent()
425 ced->resume = sh_tmu_clock_event_resume; in sh_tmu_register_clockevent()
427 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", in sh_tmu_register_clockevent()
428 ch->index); in sh_tmu_register_clockevent()
430 clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); in sh_tmu_register_clockevent()
432 ret = request_irq(ch->irq, sh_tmu_interrupt, in sh_tmu_register_clockevent()
434 dev_name(&ch->tmu->pdev->dev), ch); in sh_tmu_register_clockevent()
436 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", in sh_tmu_register_clockevent()
437 ch->index, ch->irq); in sh_tmu_register_clockevent()
442 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, in sh_tmu_register() argument
446 ch->tmu->has_clockevent = true; in sh_tmu_register()
447 sh_tmu_register_clockevent(ch, name); in sh_tmu_register()
449 ch->tmu->has_clocksource = true; in sh_tmu_register()
450 sh_tmu_register_clocksource(ch, name); in sh_tmu_register()
456 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, in sh_tmu_channel_setup() argument
464 ch->tmu = tmu; in sh_tmu_channel_setup()
465 ch->index = index; in sh_tmu_channel_setup()
467 if (tmu->model == SH_TMU_SH3) in sh_tmu_channel_setup()
468 ch->base = tmu->mapbase + 4 + ch->index * 12; in sh_tmu_channel_setup()
470 ch->base = tmu->mapbase + 8 + ch->index * 12; in sh_tmu_channel_setup()
472 ch->irq = platform_get_irq(tmu->pdev, index); in sh_tmu_channel_setup()
473 if (ch->irq < 0) { in sh_tmu_channel_setup()
474 dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n", in sh_tmu_channel_setup()
475 ch->index); in sh_tmu_channel_setup()
476 return ch->irq; in sh_tmu_channel_setup()
479 ch->cs_enabled = false; in sh_tmu_channel_setup()
480 ch->enable_count = 0; in sh_tmu_channel_setup()
482 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), in sh_tmu_channel_setup()
490 res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); in sh_tmu_map_memory()
492 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n"); in sh_tmu_map_memory()
493 return -ENXIO; in sh_tmu_map_memory()
496 tmu->mapbase = ioremap_nocache(res->start, resource_size(res)); in sh_tmu_map_memory()
497 if (tmu->mapbase == NULL) in sh_tmu_map_memory()
498 return -ENXIO; in sh_tmu_map_memory()
505 struct device_node *np = tmu->pdev->dev.of_node; in sh_tmu_parse_dt()
507 tmu->model = SH_TMU; in sh_tmu_parse_dt()
508 tmu->num_channels = 3; in sh_tmu_parse_dt()
510 of_property_read_u32(np, "#renesas,channels", &tmu->num_channels); in sh_tmu_parse_dt()
512 if (tmu->num_channels != 2 && tmu->num_channels != 3) { in sh_tmu_parse_dt()
513 dev_err(&tmu->pdev->dev, "invalid number of channels %u\n", in sh_tmu_parse_dt()
514 tmu->num_channels); in sh_tmu_parse_dt()
515 return -EINVAL; in sh_tmu_parse_dt()
526 tmu->pdev = pdev; in sh_tmu_setup()
528 raw_spin_lock_init(&tmu->lock); in sh_tmu_setup()
530 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { in sh_tmu_setup()
534 } else if (pdev->dev.platform_data) { in sh_tmu_setup()
535 const struct platform_device_id *id = pdev->id_entry; in sh_tmu_setup()
536 struct sh_timer_config *cfg = pdev->dev.platform_data; in sh_tmu_setup()
538 tmu->model = id->driver_data; in sh_tmu_setup()
539 tmu->num_channels = hweight8(cfg->channels_mask); in sh_tmu_setup()
541 dev_err(&tmu->pdev->dev, "missing platform data\n"); in sh_tmu_setup()
542 return -ENXIO; in sh_tmu_setup()
546 tmu->clk = clk_get(&tmu->pdev->dev, "fck"); in sh_tmu_setup()
547 if (IS_ERR(tmu->clk)) { in sh_tmu_setup()
548 dev_err(&tmu->pdev->dev, "cannot get clock\n"); in sh_tmu_setup()
549 return PTR_ERR(tmu->clk); in sh_tmu_setup()
552 ret = clk_prepare(tmu->clk); in sh_tmu_setup()
557 ret = clk_enable(tmu->clk); in sh_tmu_setup()
561 tmu->rate = clk_get_rate(tmu->clk) / 4; in sh_tmu_setup()
562 clk_disable(tmu->clk); in sh_tmu_setup()
567 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n"); in sh_tmu_setup()
572 tmu->channels = kcalloc(tmu->num_channels, sizeof(*tmu->channels), in sh_tmu_setup()
574 if (tmu->channels == NULL) { in sh_tmu_setup()
575 ret = -ENOMEM; in sh_tmu_setup()
583 for (i = 0; i < tmu->num_channels; ++i) { in sh_tmu_setup()
584 ret = sh_tmu_channel_setup(&tmu->channels[i], i, in sh_tmu_setup()
595 kfree(tmu->channels); in sh_tmu_setup()
596 iounmap(tmu->mapbase); in sh_tmu_setup()
598 clk_unprepare(tmu->clk); in sh_tmu_setup()
600 clk_put(tmu->clk); in sh_tmu_setup()
610 pm_runtime_set_active(&pdev->dev); in sh_tmu_probe()
611 pm_runtime_enable(&pdev->dev); in sh_tmu_probe()
615 dev_info(&pdev->dev, "kept as earlytimer\n"); in sh_tmu_probe()
621 return -ENOMEM; in sh_tmu_probe()
626 pm_runtime_idle(&pdev->dev); in sh_tmu_probe()
633 if (tmu->has_clockevent || tmu->has_clocksource) in sh_tmu_probe()
634 pm_runtime_irq_safe(&pdev->dev); in sh_tmu_probe()
636 pm_runtime_idle(&pdev->dev); in sh_tmu_probe()
643 return -EBUSY; /* cannot unregister clockevent and clocksource */ in sh_tmu_remove()
647 { "sh-tmu", SH_TMU },
648 { "sh-tmu-sh3", SH_TMU_SH3 },