Lines Matching +full:clk +full:- +full:delay +full:- +full:cycles
1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
21 #include <linux/delay.h>
76 * - aspeed timer overflow interrupt is controlled by bits in Control
78 * - aspeed timers always generate interrupt when either one of the
106 * A local singleton used by sched_clock and delay timer reads, which are
118 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
123 return ~readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_down()
136 static int fttmr010_timer_set_next_event(unsigned long cycles, in fttmr010_timer_set_next_event() argument
143 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
144 cr &= ~fttmr010->t1_enable_val; in fttmr010_timer_set_next_event()
145 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
147 if (fttmr010->is_aspeed) { in fttmr010_timer_set_next_event()
150 * into TIMER1_COUNT register when the timer is re-enabled. in fttmr010_timer_set_next_event()
152 writel(cycles, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_next_event()
155 cr = readl(fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_next_event()
156 writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); in fttmr010_timer_set_next_event()
160 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
161 cr |= fttmr010->t1_enable_val; in fttmr010_timer_set_next_event()
162 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
173 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
174 cr &= ~fttmr010->t1_enable_val; in fttmr010_timer_shutdown()
175 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
186 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_oneshot()
187 cr &= ~fttmr010->t1_enable_val; in fttmr010_timer_set_oneshot()
188 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_oneshot()
191 writel(0, fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_oneshot()
192 if (fttmr010->is_aspeed) { in fttmr010_timer_set_oneshot()
193 writel(~0, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_oneshot()
195 writel(0, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_oneshot()
198 cr = readl(fttmr010->base + TIMER_INTR_MASK); in fttmr010_timer_set_oneshot()
201 writel(cr, fttmr010->base + TIMER_INTR_MASK); in fttmr010_timer_set_oneshot()
210 u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ); in fttmr010_timer_set_periodic()
214 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_periodic()
215 cr &= ~fttmr010->t1_enable_val; in fttmr010_timer_set_periodic()
216 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_periodic()
219 if (fttmr010->is_aspeed) { in fttmr010_timer_set_periodic()
220 writel(period, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_periodic()
222 cr = 0xffffffff - (period - 1); in fttmr010_timer_set_periodic()
223 writel(cr, fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_periodic()
224 writel(cr, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_periodic()
227 cr = readl(fttmr010->base + TIMER_INTR_MASK); in fttmr010_timer_set_periodic()
230 writel(cr, fttmr010->base + TIMER_INTR_MASK); in fttmr010_timer_set_periodic()
234 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_periodic()
235 cr |= fttmr010->t1_enable_val; in fttmr010_timer_set_periodic()
236 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_periodic()
248 evt->event_handler(evt); in fttmr010_timer_interrupt()
256 struct clk *clk; in fttmr010_common_init() local
265 clk = of_clk_get_by_name(np, "PCLK"); in fttmr010_common_init()
266 if (IS_ERR(clk)) { in fttmr010_common_init()
268 return PTR_ERR(clk); in fttmr010_common_init()
270 ret = clk_prepare_enable(clk); in fttmr010_common_init()
278 ret = -ENOMEM; in fttmr010_common_init()
281 fttmr010->tick_rate = clk_get_rate(clk); in fttmr010_common_init()
283 fttmr010->base = of_iomap(np, 0); in fttmr010_common_init()
284 if (!fttmr010->base) { in fttmr010_common_init()
286 ret = -ENXIO; in fttmr010_common_init()
293 ret = -EINVAL; in fttmr010_common_init()
301 fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE | in fttmr010_common_init()
303 fttmr010->is_aspeed = true; in fttmr010_common_init()
305 fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT; in fttmr010_common_init()
310 writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); in fttmr010_common_init()
311 writel(0, fttmr010->base + TIMER_INTR_STATE); in fttmr010_common_init()
324 writel(val, fttmr010->base + TIMER_CR); in fttmr010_common_init()
327 * Setup free-running clocksource timer (interrupts in fttmr010_common_init()
331 writel(0, fttmr010->base + TIMER2_COUNT); in fttmr010_common_init()
332 writel(0, fttmr010->base + TIMER2_MATCH1); in fttmr010_common_init()
333 writel(0, fttmr010->base + TIMER2_MATCH2); in fttmr010_common_init()
335 if (fttmr010->is_aspeed) { in fttmr010_common_init()
336 writel(~0, fttmr010->base + TIMER2_LOAD); in fttmr010_common_init()
337 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, in fttmr010_common_init()
338 "FTTMR010-TIMER2", in fttmr010_common_init()
339 fttmr010->tick_rate, in fttmr010_common_init()
342 fttmr010->tick_rate); in fttmr010_common_init()
344 writel(0, fttmr010->base + TIMER2_LOAD); in fttmr010_common_init()
345 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, in fttmr010_common_init()
346 "FTTMR010-TIMER2", in fttmr010_common_init()
347 fttmr010->tick_rate, in fttmr010_common_init()
350 fttmr010->tick_rate); in fttmr010_common_init()
354 * Setup clockevent timer (interrupt-driven) on timer 1. in fttmr010_common_init()
356 writel(0, fttmr010->base + TIMER1_COUNT); in fttmr010_common_init()
357 writel(0, fttmr010->base + TIMER1_LOAD); in fttmr010_common_init()
358 writel(0, fttmr010->base + TIMER1_MATCH1); in fttmr010_common_init()
359 writel(0, fttmr010->base + TIMER1_MATCH2); in fttmr010_common_init()
361 "FTTMR010-TIMER1", &fttmr010->clkevt); in fttmr010_common_init()
363 pr_err("FTTMR010-TIMER1 no IRQ\n"); in fttmr010_common_init()
367 fttmr010->clkevt.name = "FTTMR010-TIMER1"; in fttmr010_common_init()
369 fttmr010->clkevt.rating = 300; in fttmr010_common_init()
370 fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | in fttmr010_common_init()
372 fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event; in fttmr010_common_init()
373 fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown; in fttmr010_common_init()
374 fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic; in fttmr010_common_init()
375 fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot; in fttmr010_common_init()
376 fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown; in fttmr010_common_init()
377 fttmr010->clkevt.cpumask = cpumask_of(0); in fttmr010_common_init()
378 fttmr010->clkevt.irq = irq; in fttmr010_common_init()
379 clockevents_config_and_register(&fttmr010->clkevt, in fttmr010_common_init()
380 fttmr010->tick_rate, in fttmr010_common_init()
385 if (fttmr010->is_aspeed) in fttmr010_common_init()
386 fttmr010->delay_timer.read_current_timer = in fttmr010_common_init()
389 fttmr010->delay_timer.read_current_timer = in fttmr010_common_init()
391 fttmr010->delay_timer.freq = fttmr010->tick_rate; in fttmr010_common_init()
392 register_current_timer_delay(&fttmr010->delay_timer); in fttmr010_common_init()
398 iounmap(fttmr010->base); in fttmr010_common_init()
402 clk_disable_unprepare(clk); in fttmr010_common_init()
418 TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
419 TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
420 TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
421 TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);