1 // SPDX-License-Identifier: GPL-2.0+
3 //  Copyright (C) 2000-2001 Deep Blue Solutions
5 //  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
23  *  - MX1/MXL
24  *  - MX21, MX27.
25  *  - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
26  *  - MX6DL, MX6SX, MX6Q(rev1.1+)
68 	const struct imx_gpt_data *gpt;  member
94 	tmp = readl_relaxed(imxtm->base + MXC_TCTL);  in imx1_gpt_irq_disable()
95 	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);  in imx1_gpt_irq_disable()
101 	writel_relaxed(0, imxtm->base + V2_IR);  in imx31_gpt_irq_disable()
109 	tmp = readl_relaxed(imxtm->base + MXC_TCTL);  in imx1_gpt_irq_enable()
110 	writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);  in imx1_gpt_irq_enable()
116 	writel_relaxed(1<<0, imxtm->base + V2_IR);  in imx31_gpt_irq_enable()
122 	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);  in imx1_gpt_irq_acknowledge()
128 				imxtm->base + MX1_2_TSTAT);  in imx21_gpt_irq_acknowledge()
133 	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);  in imx31_gpt_irq_acknowledge()
153 	unsigned int c = clk_get_rate(imxtm->clk_per);  in mxc_clocksource_init()
154 	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;  in mxc_clocksource_init()
175 	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;  in mx1_2_set_next_event()
177 	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);  in mx1_2_set_next_event()
179 	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?  in mx1_2_set_next_event()
180 				-ETIME : 0;  in mx1_2_set_next_event()
189 	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;  in v2_set_next_event()
191 	writel_relaxed(tcmp, imxtm->base + V2_TCMP);  in v2_set_next_event()
194 		(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?  in v2_set_next_event()
195 				-ETIME : 0;  in v2_set_next_event()
210 	/* Disable interrupt in GPT module */  in mxc_shutdown()
211 	imxtm->gpt->gpt_irq_disable(imxtm);  in mxc_shutdown()
213 	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);  in mxc_shutdown()
214 	/* Set event time into far-far future */  in mxc_shutdown()
215 	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);  in mxc_shutdown()
218 	imxtm->gpt->gpt_irq_acknowledge(imxtm);  in mxc_shutdown()
240 	/* Disable interrupt in GPT module */  in mxc_set_oneshot()
241 	imxtm->gpt->gpt_irq_disable(imxtm);  in mxc_set_oneshot()
244 		u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);  in mxc_set_oneshot()
245 		/* Set event time into far-far future */  in mxc_set_oneshot()
246 		writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);  in mxc_set_oneshot()
249 		imxtm->gpt->gpt_irq_acknowledge(imxtm);  in mxc_set_oneshot()
262 	imxtm->gpt->gpt_irq_enable(imxtm);  in mxc_set_oneshot()
277 	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);  in mxc_timer_interrupt()
279 	imxtm->gpt->gpt_irq_acknowledge(imxtm);  in mxc_timer_interrupt()
281 	ced->event_handler(ced);  in mxc_timer_interrupt()
288 	struct clock_event_device *ced = &imxtm->ced;  in mxc_clockevent_init()
289 	struct irqaction *act = &imxtm->act;  in mxc_clockevent_init()
291 	ced->name = "mxc_timer1";  in mxc_clockevent_init()
292 	ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;  in mxc_clockevent_init()
293 	ced->set_state_shutdown = mxc_shutdown;  in mxc_clockevent_init()
294 	ced->set_state_oneshot = mxc_set_oneshot;  in mxc_clockevent_init()
295 	ced->tick_resume = mxc_shutdown;  in mxc_clockevent_init()
296 	ced->set_next_event = imxtm->gpt->set_next_event;  in mxc_clockevent_init()
297 	ced->rating = 200;  in mxc_clockevent_init()
298 	ced->cpumask = cpumask_of(0);  in mxc_clockevent_init()
299 	ced->irq = imxtm->irq;  in mxc_clockevent_init()
300 	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),  in mxc_clockevent_init()
303 	act->name = "i.MX Timer Tick";  in mxc_clockevent_init()
304 	act->flags = IRQF_TIMER | IRQF_IRQPOLL;  in mxc_clockevent_init()
305 	act->handler = mxc_timer_interrupt;  in mxc_clockevent_init()
306 	act->dev_id = ced;  in mxc_clockevent_init()
308 	return setup_irq(imxtm->irq, act);  in mxc_clockevent_init()
316 	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);  in imx1_gpt_setup_tctl()
325 	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)  in imx31_gpt_setup_tctl()
330 	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);  in imx31_gpt_setup_tctl()
338 	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {  in imx6dl_gpt_setup_tctl()
341 		writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);  in imx6dl_gpt_setup_tctl()
347 	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);  in imx6dl_gpt_setup_tctl()
398 	switch (imxtm->type) {  in _mxc_timer_init()
400 		imxtm->gpt = &imx1_gpt_data;  in _mxc_timer_init()
403 		imxtm->gpt = &imx21_gpt_data;  in _mxc_timer_init()
406 		imxtm->gpt = &imx31_gpt_data;  in _mxc_timer_init()
409 		imxtm->gpt = &imx6dl_gpt_data;  in _mxc_timer_init()
412 		return -EINVAL;  in _mxc_timer_init()
415 	if (IS_ERR(imxtm->clk_per)) {  in _mxc_timer_init()
417 		return PTR_ERR(imxtm->clk_per);  in _mxc_timer_init()
420 	if (!IS_ERR(imxtm->clk_ipg))  in _mxc_timer_init()
421 		clk_prepare_enable(imxtm->clk_ipg);  in _mxc_timer_init()
423 	clk_prepare_enable(imxtm->clk_per);  in _mxc_timer_init()
429 	writel_relaxed(0, imxtm->base + MXC_TCTL);  in _mxc_timer_init()
430 	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */  in _mxc_timer_init()
432 	imxtm->gpt->gpt_setup_tctl(imxtm);  in _mxc_timer_init()
449 	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");  in mxc_timer_init()
450 	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");  in mxc_timer_init()
452 	imxtm->base = ioremap(pbase, SZ_4K);  in mxc_timer_init()
453 	BUG_ON(!imxtm->base);  in mxc_timer_init()
455 	imxtm->type = type;  in mxc_timer_init()
456 	imxtm->irq = irq;  in mxc_timer_init()
473 		return -ENOMEM;  in mxc_timer_init_dt()
475 	imxtm->base = of_iomap(np, 0);  in mxc_timer_init_dt()
476 	if (!imxtm->base)  in mxc_timer_init_dt()
477 		return -ENXIO;  in mxc_timer_init_dt()
479 	imxtm->irq = irq_of_parse_and_map(np, 0);  in mxc_timer_init_dt()
480 	if (imxtm->irq <= 0)  in mxc_timer_init_dt()
481 		return -EINVAL;  in mxc_timer_init_dt()
483 	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");  in mxc_timer_init_dt()
486 	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");  in mxc_timer_init_dt()
487 	if (IS_ERR(imxtm->clk_per))  in mxc_timer_init_dt()
488 		imxtm->clk_per = of_clk_get_by_name(np, "per");  in mxc_timer_init_dt()
490 	imxtm->type = type;  in mxc_timer_init_dt()
517 	 * GPT device, while they actually have different programming model.  in imx31_timer_init_dt()
532 TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
533 TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
534 TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
535 TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
536 TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
537 TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
538 TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
539 TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
540 TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
541 TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
542 TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
543 TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);