Lines Matching +full:0 +full:x0000003f

45 #define CPUID_XFAM			0x0ff00000	/* extended family */
46 #define CPUID_XFAM_K8			0
47 #define CPUID_XMOD			0x000f0000	/* extended model */
48 #define CPUID_XMOD_REV_MASK		0x000c0000
49 #define CPUID_XFAM_10H			0x00100000	/* family 0x10 */
50 #define CPUID_USE_XFAM_XMOD		0x00000f00
51 #define CPUID_GET_MAX_CAPABILITIES	0x80000000
52 #define CPUID_FREQ_VOLT_CAPABILITIES	0x80000007
56 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
57 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
60 #define MSR_FIDVID_CTL      0xc0010041
61 #define MSR_FIDVID_STATUS   0xc0010042
64 #define MSR_C_LO_INIT_FID_VID     0x00010000
65 #define MSR_C_LO_NEW_VID          0x00003f00
66 #define MSR_C_LO_NEW_FID          0x0000003f
70 #define MSR_C_HI_STP_GNT_TO	  0x000fffff
73 #define MSR_S_LO_CHANGE_PENDING   0x80000000   /* cleared when completed */
74 #define MSR_S_LO_MAX_RAMP_VID     0x3f000000
75 #define MSR_S_LO_MAX_FID          0x003f0000
76 #define MSR_S_LO_START_FID        0x00003f00
77 #define MSR_S_LO_CURRENT_FID      0x0000003f
80 #define MSR_S_HI_MIN_WORKING_VID  0x3f000000
81 #define MSR_S_HI_MAX_WORKING_VID  0x003f0000
82 #define MSR_S_HI_START_VID        0x00003f00
83 #define MSR_S_HI_CURRENT_VID      0x0000003f
84 #define MSR_C_HI_STP_GNT_BENIGN	  0x00000001
108 #define MAX_FID 0x2a	/* Spec only gives FID values as far as 5 GHz */
109 #define LEAST_VID 0x3e	/* Lowest (numerically highest) useful vid value */
114 #define INVALID_FID_MASK 0xffffffc0  /* not a valid fid if these bits are set */
115 #define INVALID_VID_MASK 0xffffffc0  /* not a valid vid if these bits are set */
117 #define VID_OFF 0x3f
141 #define PLL_L_MASK   0x7f
143 #define VST_MASK     0x7f
144 #define VID_MASK     0x1f
145 #define FID_MASK     0x1f
146 #define EXT_VID_MASK 0x3f
147 #define EXT_FID_MASK 0x3f
161 #define PSB_VERSION_1_4  0x14