Lines Matching +full:clkdiv +full:- +full:-
2 * Copyright (c) 2006-2008 Simtec Electronics
26 #include <mach/regs-clock.h>
29 #include <plat/cpu-freq-core.h>
31 /* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
35 u32 clkdiv = 0; in s3c2410_cpufreq_setdivs() local
37 if (cfg->divs.h_divisor == 2) in s3c2410_cpufreq_setdivs()
38 clkdiv |= S3C2410_CLKDIVN_HDIVN; in s3c2410_cpufreq_setdivs()
40 if (cfg->divs.p_divisor != cfg->divs.h_divisor) in s3c2410_cpufreq_setdivs()
41 clkdiv |= S3C2410_CLKDIVN_PDIVN; in s3c2410_cpufreq_setdivs()
43 __raw_writel(clkdiv, S3C2410_CLKDIVN); in s3c2410_cpufreq_setdivs()
52 fclk = cfg->freq.fclk; in s3c2410_cpufreq_calcdivs()
53 hclk_max = cfg->max.hclk; in s3c2410_cpufreq_calcdivs()
55 cfg->freq.armclk = fclk; in s3c2410_cpufreq_calcdivs()
60 hdiv = (fclk > cfg->max.hclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
63 if (hclk > cfg->max.hclk) { in s3c2410_cpufreq_calcdivs()
65 return -EINVAL; in s3c2410_cpufreq_calcdivs()
68 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
71 if (pclk > cfg->max.pclk) { in s3c2410_cpufreq_calcdivs()
73 return -EINVAL; in s3c2410_cpufreq_calcdivs()
79 cfg->divs.p_divisor = pdiv; in s3c2410_cpufreq_calcdivs()
80 cfg->divs.h_divisor = hdiv; in s3c2410_cpufreq_calcdivs()
92 /* transition latency is about 5ms worst-case, so