19 #define DRIVER_NAME             "stm32-crc32"
68 	mctx->key = 0;  in stm32_crc32_cra_init()
69 	mctx->poly = CRC32_POLY_LE;  in stm32_crc32_cra_init()
77 	mctx->key = CRC32C_INIT_DEFAULT;  in stm32_crc32c_cra_init()
78 	mctx->poly = CRC32C_POLY_LE;  in stm32_crc32c_cra_init()
89 		return -EINVAL;  in stm32_crc_setkey()
92 	mctx->key = get_unaligned_le32(key);  in stm32_crc_setkey()
98 	struct stm32_crc *crc;  in stm32_crc_get_next_crc()  local
101 	crc = list_first_entry(&crc_list.dev_list, struct stm32_crc, list);  in stm32_crc_get_next_crc()
102 	if (crc)  in stm32_crc_get_next_crc()
103 		list_move_tail(&crc->list, &crc_list.dev_list);  in stm32_crc_get_next_crc()
106 	return crc;  in stm32_crc_get_next_crc()
112 	struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);  in stm32_crc_init()
113 	struct stm32_crc *crc;  in stm32_crc_init()  local
115 	crc = stm32_crc_get_next_crc();  in stm32_crc_init()
116 	if (!crc)  in stm32_crc_init()
117 		return -ENODEV;  in stm32_crc_init()
119 	pm_runtime_get_sync(crc->dev);  in stm32_crc_init()
122 	writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);  in stm32_crc_init()
123 	writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);  in stm32_crc_init()
125 		       crc->regs + CRC_CR);  in stm32_crc_init()
128 	ctx->partial = readl_relaxed(crc->regs + CRC_DR);  in stm32_crc_init()
130 	pm_runtime_mark_last_busy(crc->dev);  in stm32_crc_init()
131 	pm_runtime_put_autosuspend(crc->dev);  in stm32_crc_init()
140 	struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);  in stm32_crc_update()
141 	struct stm32_crc *crc;  in stm32_crc_update()  local
143 	crc = stm32_crc_get_next_crc();  in stm32_crc_update()
144 	if (!crc)  in stm32_crc_update()
145 		return -ENODEV;  in stm32_crc_update()
147 	pm_runtime_get_sync(crc->dev);  in stm32_crc_update()
150 	 * Restore previously calculated CRC for this context as init value  in stm32_crc_update()
155 	writel_relaxed(bitrev32(ctx->partial), crc->regs + CRC_INIT);  in stm32_crc_update()
156 	writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);  in stm32_crc_update()
158 		       crc->regs + CRC_CR);  in stm32_crc_update()
163 			       crc->regs + CRC_CR);  in stm32_crc_update()
165 			writeb_relaxed(*d8++, crc->regs + CRC_DR);  in stm32_crc_update()
166 			length--;  in stm32_crc_update()
170 			       crc->regs + CRC_CR);  in stm32_crc_update()
173 	for (; length >= sizeof(u32); d8 += sizeof(u32), length -= sizeof(u32))  in stm32_crc_update()
174 		writel_relaxed(*((u32 *)d8), crc->regs + CRC_DR);  in stm32_crc_update()
179 			       crc->regs + CRC_CR);  in stm32_crc_update()
180 		while (length--)  in stm32_crc_update()
181 			writeb_relaxed(*d8++, crc->regs + CRC_DR);  in stm32_crc_update()
185 	ctx->partial = readl_relaxed(crc->regs + CRC_DR);  in stm32_crc_update()
187 	pm_runtime_mark_last_busy(crc->dev);  in stm32_crc_update()
188 	pm_runtime_put_autosuspend(crc->dev);  in stm32_crc_update()
196 	struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);  in stm32_crc_final()
198 	/* Send computed CRC */  in stm32_crc_final()
199 	put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?  in stm32_crc_final()
200 			   ~ctx->partial : ctx->partial, out);  in stm32_crc_final()
221 	/* CRC-32 */
243 	/* CRC-32Castagnoli */
269 	struct device *dev = &pdev->dev;  in stm32_crc_probe()
270 	struct stm32_crc *crc;  in stm32_crc_probe()  local
274 	crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);  in stm32_crc_probe()
275 	if (!crc)  in stm32_crc_probe()
276 		return -ENOMEM;  in stm32_crc_probe()
278 	crc->dev = dev;  in stm32_crc_probe()
281 	crc->regs = devm_ioremap_resource(dev, res);  in stm32_crc_probe()
282 	if (IS_ERR(crc->regs)) {  in stm32_crc_probe()
283 		dev_err(dev, "Cannot map CRC IO\n");  in stm32_crc_probe()
284 		return PTR_ERR(crc->regs);  in stm32_crc_probe()
287 	crc->clk = devm_clk_get(dev, NULL);  in stm32_crc_probe()
288 	if (IS_ERR(crc->clk)) {  in stm32_crc_probe()
290 		return PTR_ERR(crc->clk);  in stm32_crc_probe()
293 	ret = clk_prepare_enable(crc->clk);  in stm32_crc_probe()
295 		dev_err(crc->dev, "Failed to enable clock\n");  in stm32_crc_probe()
306 	platform_set_drvdata(pdev, crc);  in stm32_crc_probe()
309 	list_add(&crc->list, &crc_list.dev_list);  in stm32_crc_probe()
318 			clk_disable_unprepare(crc->clk);  in stm32_crc_probe()
334 	struct stm32_crc *crc = platform_get_drvdata(pdev);  in stm32_crc_remove()  local
335 	int ret = pm_runtime_get_sync(crc->dev);  in stm32_crc_remove()
341 	list_del(&crc->list);  in stm32_crc_remove()
345 	if (!--refcnt)  in stm32_crc_remove()
349 	pm_runtime_disable(crc->dev);  in stm32_crc_remove()
350 	pm_runtime_put_noidle(crc->dev);  in stm32_crc_remove()
352 	clk_disable_unprepare(crc->clk);  in stm32_crc_remove()
360 	struct stm32_crc *crc = dev_get_drvdata(dev);  in stm32_crc_runtime_suspend()  local
362 	clk_disable_unprepare(crc->clk);  in stm32_crc_runtime_suspend()
369 	struct stm32_crc *crc = dev_get_drvdata(dev);  in stm32_crc_runtime_resume()  local
372 	ret = clk_prepare_enable(crc->clk);  in stm32_crc_runtime_resume()
374 		dev_err(crc->dev, "Failed to prepare_enable clock\n");  in stm32_crc_runtime_resume()
390 	{ .compatible = "st,stm32f7-crc", },