Lines Matching full:bus
2 * Generic Exynos Bus frequency driver with DEVFREQ Framework
7 * This driver support Exynos Bus frequency feature by using
47 * Control the devfreq-event device to get the current state of bus
50 static int exynos_bus_##ops(struct exynos_bus *bus) \
54 for (i = 0; i < bus->edev_count; i++) { \
55 if (!bus->edev[i]) \
57 ret = devfreq_event_##ops(bus->edev[i]); \
68 static int exynos_bus_get_event(struct exynos_bus *bus, in exynos_bus_get_event() argument
75 for (i = 0; i < bus->edev_count; i++) { in exynos_bus_get_event()
76 if (!bus->edev[i]) in exynos_bus_get_event()
79 ret = devfreq_event_get_event(bus->edev[i], &event_data); in exynos_bus_get_event()
100 struct exynos_bus *bus = dev_get_drvdata(dev); in exynos_bus_target() local
105 /* Get new opp-bus instance according to new bus clock */ in exynos_bus_target()
116 old_freq = bus->curr_freq; in exynos_bus_target()
120 tol = new_volt * bus->voltage_tolerance / 100; in exynos_bus_target()
123 mutex_lock(&bus->lock); in exynos_bus_target()
126 ret = regulator_set_voltage_tol(bus->regulator, new_volt, tol); in exynos_bus_target()
128 dev_err(bus->dev, "failed to set voltage\n"); in exynos_bus_target()
133 ret = clk_set_rate(bus->clk, new_freq); in exynos_bus_target()
135 dev_err(dev, "failed to change clock of bus\n"); in exynos_bus_target()
136 clk_set_rate(bus->clk, old_freq); in exynos_bus_target()
141 ret = regulator_set_voltage_tol(bus->regulator, new_volt, tol); in exynos_bus_target()
143 dev_err(bus->dev, "failed to set voltage\n"); in exynos_bus_target()
147 bus->curr_freq = new_freq; in exynos_bus_target()
149 dev_dbg(dev, "Set the frequency of bus (%luHz -> %luHz, %luHz)\n", in exynos_bus_target()
150 old_freq, new_freq, clk_get_rate(bus->clk)); in exynos_bus_target()
152 mutex_unlock(&bus->lock); in exynos_bus_target()
160 struct exynos_bus *bus = dev_get_drvdata(dev); in exynos_bus_get_dev_status() local
164 stat->current_frequency = bus->curr_freq; in exynos_bus_get_dev_status()
166 ret = exynos_bus_get_event(bus, &edata); in exynos_bus_get_dev_status()
172 stat->busy_time = (edata.load_count * 100) / bus->ratio; in exynos_bus_get_dev_status()
179 ret = exynos_bus_set_event(bus); in exynos_bus_get_dev_status()
190 struct exynos_bus *bus = dev_get_drvdata(dev); in exynos_bus_exit() local
193 ret = exynos_bus_disable_edev(bus); in exynos_bus_exit()
198 clk_disable_unprepare(bus->clk); in exynos_bus_exit()
199 if (bus->regulator) in exynos_bus_exit()
200 regulator_disable(bus->regulator); in exynos_bus_exit()
209 struct exynos_bus *bus = dev_get_drvdata(dev); in exynos_bus_passive_target() local
214 /* Get new opp-bus instance according to new bus clock */ in exynos_bus_passive_target()
224 old_freq = bus->curr_freq; in exynos_bus_passive_target()
230 mutex_lock(&bus->lock); in exynos_bus_passive_target()
232 ret = clk_set_rate(bus->clk, new_freq); in exynos_bus_passive_target()
234 dev_err(dev, "failed to set the clock of bus\n"); in exynos_bus_passive_target()
239 bus->curr_freq = new_freq; in exynos_bus_passive_target()
241 dev_dbg(dev, "Set the frequency of bus (%luHz -> %luHz, %luHz)\n", in exynos_bus_passive_target()
242 old_freq, new_freq, clk_get_rate(bus->clk)); in exynos_bus_passive_target()
244 mutex_unlock(&bus->lock); in exynos_bus_passive_target()
251 struct exynos_bus *bus = dev_get_drvdata(dev); in exynos_bus_passive_exit() local
254 clk_disable_unprepare(bus->clk); in exynos_bus_passive_exit()
258 struct exynos_bus *bus) in exynos_bus_parent_parse_of() argument
260 struct device *dev = bus->dev; in exynos_bus_parent_parse_of()
263 /* Get the regulator to provide each bus with the power */ in exynos_bus_parent_parse_of()
264 bus->regulator = devm_regulator_get(dev, "vdd"); in exynos_bus_parent_parse_of()
265 if (IS_ERR(bus->regulator)) { in exynos_bus_parent_parse_of()
267 return PTR_ERR(bus->regulator); in exynos_bus_parent_parse_of()
270 ret = regulator_enable(bus->regulator); in exynos_bus_parent_parse_of()
286 bus->edev_count = count; in exynos_bus_parent_parse_of()
288 size = sizeof(*bus->edev) * count; in exynos_bus_parent_parse_of()
289 bus->edev = devm_kzalloc(dev, size, GFP_KERNEL); in exynos_bus_parent_parse_of()
290 if (!bus->edev) { in exynos_bus_parent_parse_of()
296 bus->edev[i] = devfreq_event_get_edev_by_phandle(dev, i); in exynos_bus_parent_parse_of()
297 if (IS_ERR(bus->edev[i])) { in exynos_bus_parent_parse_of()
305 * When measuring the utilization of each AXI bus with devfreq-event in exynos_bus_parent_parse_of()
307 * total cycle of bus during sampling rate. In result, the devfreq in exynos_bus_parent_parse_of()
313 if (of_property_read_u32(np, "exynos,saturation-ratio", &bus->ratio)) in exynos_bus_parent_parse_of()
314 bus->ratio = DEFAULT_SATURATION_RATIO; in exynos_bus_parent_parse_of()
317 &bus->voltage_tolerance)) in exynos_bus_parent_parse_of()
318 bus->voltage_tolerance = DEFAULT_VOLTAGE_TOLERANCE; in exynos_bus_parent_parse_of()
323 regulator_disable(bus->regulator); in exynos_bus_parent_parse_of()
329 struct exynos_bus *bus) in exynos_bus_parse_of() argument
331 struct device *dev = bus->dev; in exynos_bus_parse_of()
336 /* Get the clock to provide each bus with source clock */ in exynos_bus_parse_of()
337 bus->clk = devm_clk_get(dev, "bus"); in exynos_bus_parse_of()
338 if (IS_ERR(bus->clk)) { in exynos_bus_parse_of()
339 dev_err(dev, "failed to get bus clock\n"); in exynos_bus_parse_of()
340 return PTR_ERR(bus->clk); in exynos_bus_parse_of()
343 ret = clk_prepare_enable(bus->clk); in exynos_bus_parse_of()
349 /* Get the freq and voltage from OPP table to scale the bus freq */ in exynos_bus_parse_of()
356 rate = clk_get_rate(bus->clk); in exynos_bus_parse_of()
364 bus->curr_freq = dev_pm_opp_get_freq(opp); in exynos_bus_parse_of()
372 clk_disable_unprepare(bus->clk); in exynos_bus_parse_of()
385 struct exynos_bus *bus; in exynos_bus_probe() local
395 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); in exynos_bus_probe()
396 if (!bus) in exynos_bus_probe()
398 mutex_init(&bus->lock); in exynos_bus_probe()
399 bus->dev = &pdev->dev; in exynos_bus_probe()
400 platform_set_drvdata(pdev, bus); in exynos_bus_probe()
411 ret = exynos_bus_parent_parse_of(np, bus); in exynos_bus_probe()
417 ret = exynos_bus_parse_of(np, bus); in exynos_bus_probe()
438 /* Add devfreq device to monitor and handle the exynos bus */ in exynos_bus_probe()
439 bus->devfreq = devm_devfreq_add_device(dev, profile, in exynos_bus_probe()
442 if (IS_ERR(bus->devfreq)) { in exynos_bus_probe()
444 ret = PTR_ERR(bus->devfreq); in exynos_bus_probe()
449 ret = devm_devfreq_register_opp_notifier(dev, bus->devfreq); in exynos_bus_probe()
457 * current bus load. in exynos_bus_probe()
459 ret = exynos_bus_enable_edev(bus); in exynos_bus_probe()
465 ret = exynos_bus_set_event(bus); in exynos_bus_probe()
491 /* Add devfreq device for exynos bus with passive governor */ in exynos_bus_probe()
492 bus->devfreq = devm_devfreq_add_device(dev, profile, DEVFREQ_GOV_PASSIVE, in exynos_bus_probe()
494 if (IS_ERR(bus->devfreq)) { in exynos_bus_probe()
497 ret = PTR_ERR(bus->devfreq); in exynos_bus_probe()
502 max_state = bus->devfreq->profile->max_state; in exynos_bus_probe()
503 min_freq = (bus->devfreq->profile->freq_table[0] / 1000); in exynos_bus_probe()
504 max_freq = (bus->devfreq->profile->freq_table[max_state - 1] / 1000); in exynos_bus_probe()
505 pr_info("exynos-bus: new bus device registered: %s (%6ld KHz ~ %6ld KHz)\n", in exynos_bus_probe()
512 clk_disable_unprepare(bus->clk); in exynos_bus_probe()
515 regulator_disable(bus->regulator); in exynos_bus_probe()
523 struct exynos_bus *bus = dev_get_drvdata(dev); in exynos_bus_resume() local
526 ret = exynos_bus_enable_edev(bus); in exynos_bus_resume()
537 struct exynos_bus *bus = dev_get_drvdata(dev); in exynos_bus_suspend() local
540 ret = exynos_bus_disable_edev(bus); in exynos_bus_suspend()
555 { .compatible = "samsung,exynos-bus", },
563 .name = "exynos-bus",
570 MODULE_DESCRIPTION("Generic Exynos Bus frequency driver");