Lines Matching +full:address +full:- +full:width
2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
113 u32 mr; /* 0x00 - Mode Register */
114 u32 sr; /* 0x04 - Status Register */
115 u64 cdar; /* 0x08 - Current descriptor address register */
116 u64 sar; /* 0x10 - Source Address Register */
117 u64 dar; /* 0x18 - Destination Address Register */
118 u32 bcr; /* 0x20 - Byte Count Register */
119 u64 ndar; /* 0x24 - Next Descriptor Address Register */
134 /* Define macros for fsldma_chan->feature property */
226 #define DMA_IN(fsl_chan, addr, width) \ argument
227 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
228 in_be##width(addr) : in_le##width(addr))
229 #define DMA_OUT(fsl_chan, addr, val, width) \ argument
230 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
231 out_be##width(addr, val) : out_le##width(addr, val))
233 #define DMA_TO_CPU(fsl_chan, d, width) \ argument
234 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
235 be##width##_to_cpu((__force __be##width)(v##width)d) : \
236 le##width##_to_cpu((__force __le##width)(v##width)d))
237 #define CPU_TO_DMA(fsl_chan, c, width) \ argument
238 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
239 (__force v##width)cpu_to_be##width(c) : \
240 (__force v##width)cpu_to_le##width(c))