Lines Matching +full:imx35 +full:- +full:spdif
1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
26 #include <linux/dma-mapping.h>
38 #include <linux/platform_data/dma-imx-sdma.h>
39 #include <linux/platform_data/dma-imx.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
45 #include "virt-dma.h"
129 * 0-7 Lower WML Lower watermark level
134 * 10 SPDIF If this bit is set both source
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
153 * 30 --------- MUST BE 0
185 * Mode/Count of data node descriptors - IPCv2
204 * struct sdma_channel_control - Channel control Block
218 * struct sdma_state_registers - SDMA context for a channel
247 * struct sdma_context_data - sdma context specific to a channel
305 * struct sdma_desc - descriptor structor for one transfer
312 * @chn_real_count: the real count updated from bd->mode.count
331 * struct sdma_channel - housekeeping for a SDMA channel
394 * struct sdma_firmware_header - Layout of the firmware image
559 .name = "imx25-sdma",
562 .name = "imx31-sdma",
565 .name = "imx35-sdma",
568 .name = "imx51-sdma",
571 .name = "imx53-sdma",
574 .name = "imx6q-sdma",
577 .name = "imx7d-sdma",
586 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
587 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
588 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
589 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
590 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
591 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
592 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
598 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
604 u32 chnenbl0 = sdma->drvdata->chnenbl0; in chnenbl_ofs()
611 struct sdma_engine *sdma = sdmac->sdma; in sdma_config_ownership()
612 int channel = sdmac->channel; in sdma_config_ownership()
616 return -EINVAL; in sdma_config_ownership()
618 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
619 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
620 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
637 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
638 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
639 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
646 writel(BIT(channel), sdma->regs + SDMA_H_START); in sdma_enable_channel()
650 * sdma_run_channel0 - run a channel and wait till it's done
659 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, in sdma_run_channel0()
662 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); in sdma_run_channel0()
665 if (readl(sdma->regs + SDMA_H_CONFIG) == 0) in sdma_run_channel0()
666 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
674 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_script()
684 return -ENOMEM; in sdma_load_script()
687 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_script()
689 bd0->mode.command = C0_SETPM; in sdma_load_script()
690 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_script()
691 bd0->mode.count = size / 2; in sdma_load_script()
692 bd0->buffer_addr = buf_phys; in sdma_load_script()
693 bd0->ext_buffer_addr = address; in sdma_load_script()
699 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_script()
708 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_enable()
709 int channel = sdmac->channel; in sdma_event_enable()
713 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
715 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
720 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_disable()
721 int channel = sdmac->channel; in sdma_event_disable()
725 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
727 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
737 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); in sdma_start_desc()
739 struct sdma_engine *sdma = sdmac->sdma; in sdma_start_desc()
740 int channel = sdmac->channel; in sdma_start_desc()
743 sdmac->desc = NULL; in sdma_start_desc()
746 sdmac->desc = desc = to_sdma_desc(&vd->tx); in sdma_start_desc()
751 if (!(sdmac->flags & IMX_DMA_SG_LOOP)) in sdma_start_desc()
752 list_del(&vd->node); in sdma_start_desc()
754 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; in sdma_start_desc()
755 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; in sdma_start_desc()
756 sdma_enable_channel(sdma, sdmac->channel); in sdma_start_desc()
763 enum dma_status old_status = sdmac->status; in sdma_update_channel_loop()
766 * loop mode. Iterate over descriptors, re-setup them and in sdma_update_channel_loop()
769 while (sdmac->desc) { in sdma_update_channel_loop()
770 struct sdma_desc *desc = sdmac->desc; in sdma_update_channel_loop()
772 bd = &desc->bd[desc->buf_tail]; in sdma_update_channel_loop()
774 if (bd->mode.status & BD_DONE) in sdma_update_channel_loop()
777 if (bd->mode.status & BD_RROR) { in sdma_update_channel_loop()
778 bd->mode.status &= ~BD_RROR; in sdma_update_channel_loop()
779 sdmac->status = DMA_ERROR; in sdma_update_channel_loop()
780 error = -EIO; in sdma_update_channel_loop()
784 * We use bd->mode.count to calculate the residue, since contains in sdma_update_channel_loop()
788 desc->chn_real_count = bd->mode.count; in sdma_update_channel_loop()
789 bd->mode.status |= BD_DONE; in sdma_update_channel_loop()
790 bd->mode.count = desc->period_len; in sdma_update_channel_loop()
791 desc->buf_ptail = desc->buf_tail; in sdma_update_channel_loop()
792 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; in sdma_update_channel_loop()
800 spin_unlock(&sdmac->vc.lock); in sdma_update_channel_loop()
801 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); in sdma_update_channel_loop()
802 spin_lock(&sdmac->vc.lock); in sdma_update_channel_loop()
805 sdmac->status = old_status; in sdma_update_channel_loop()
815 sdmac->desc->chn_real_count = 0; in mxc_sdma_handle_channel_normal()
820 for (i = 0; i < sdmac->desc->num_bd; i++) { in mxc_sdma_handle_channel_normal()
821 bd = &sdmac->desc->bd[i]; in mxc_sdma_handle_channel_normal()
823 if (bd->mode.status & (BD_DONE | BD_RROR)) in mxc_sdma_handle_channel_normal()
824 error = -EIO; in mxc_sdma_handle_channel_normal()
825 sdmac->desc->chn_real_count += bd->mode.count; in mxc_sdma_handle_channel_normal()
829 sdmac->status = DMA_ERROR; in mxc_sdma_handle_channel_normal()
831 sdmac->status = DMA_COMPLETE; in mxc_sdma_handle_channel_normal()
839 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
840 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
845 int channel = fls(stat) - 1; in sdma_int_handler()
846 struct sdma_channel *sdmac = &sdma->channel[channel]; in sdma_int_handler()
849 spin_lock(&sdmac->vc.lock); in sdma_int_handler()
850 desc = sdmac->desc; in sdma_int_handler()
852 if (sdmac->flags & IMX_DMA_SG_LOOP) { in sdma_int_handler()
856 vchan_cookie_complete(&desc->vd); in sdma_int_handler()
861 spin_unlock(&sdmac->vc.lock); in sdma_int_handler()
874 struct sdma_engine *sdma = sdmac->sdma; in sdma_get_pc()
878 * two peripherals or memory-to-memory transfers in sdma_get_pc()
882 sdmac->pc_from_device = 0; in sdma_get_pc()
883 sdmac->pc_to_device = 0; in sdma_get_pc()
884 sdmac->device_to_device = 0; in sdma_get_pc()
885 sdmac->pc_to_pc = 0; in sdma_get_pc()
889 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; in sdma_get_pc()
892 emi_2_per = sdma->script_addrs->bp_2_ap_addr; in sdma_get_pc()
893 per_2_emi = sdma->script_addrs->ap_2_bp_addr; in sdma_get_pc()
896 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; in sdma_get_pc()
897 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; in sdma_get_pc()
900 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; in sdma_get_pc()
901 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
904 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; in sdma_get_pc()
905 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
908 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; in sdma_get_pc()
909 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; in sdma_get_pc()
915 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
916 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
919 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; in sdma_get_pc()
920 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; in sdma_get_pc()
928 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
929 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
932 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
933 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
934 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
937 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
938 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
939 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
942 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; in sdma_get_pc()
943 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; in sdma_get_pc()
946 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; in sdma_get_pc()
949 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; in sdma_get_pc()
950 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; in sdma_get_pc()
953 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; in sdma_get_pc()
959 sdmac->pc_from_device = per_2_emi; in sdma_get_pc()
960 sdmac->pc_to_device = emi_2_per; in sdma_get_pc()
961 sdmac->device_to_device = per_2_per; in sdma_get_pc()
962 sdmac->pc_to_pc = emi_2_emi; in sdma_get_pc()
967 struct sdma_engine *sdma = sdmac->sdma; in sdma_load_context()
968 int channel = sdmac->channel; in sdma_load_context()
970 struct sdma_context_data *context = sdma->context; in sdma_load_context()
971 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_context()
975 if (sdmac->direction == DMA_DEV_TO_MEM) in sdma_load_context()
976 load_address = sdmac->pc_from_device; in sdma_load_context()
977 else if (sdmac->direction == DMA_DEV_TO_DEV) in sdma_load_context()
978 load_address = sdmac->device_to_device; in sdma_load_context()
979 else if (sdmac->direction == DMA_MEM_TO_MEM) in sdma_load_context()
980 load_address = sdmac->pc_to_pc; in sdma_load_context()
982 load_address = sdmac->pc_to_device; in sdma_load_context()
987 dev_dbg(sdma->dev, "load_address = %d\n", load_address); in sdma_load_context()
988 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); in sdma_load_context()
989 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); in sdma_load_context()
990 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); in sdma_load_context()
991 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); in sdma_load_context()
992 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); in sdma_load_context()
994 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_context()
997 context->channel_state.pc = load_address; in sdma_load_context()
1002 context->gReg[0] = sdmac->event_mask[1]; in sdma_load_context()
1003 context->gReg[1] = sdmac->event_mask[0]; in sdma_load_context()
1004 context->gReg[2] = sdmac->per_addr; in sdma_load_context()
1005 context->gReg[6] = sdmac->shp_addr; in sdma_load_context()
1006 context->gReg[7] = sdmac->watermark_level; in sdma_load_context()
1008 bd0->mode.command = C0_SETDM; in sdma_load_context()
1009 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_context()
1010 bd0->mode.count = sizeof(*context) / 4; in sdma_load_context()
1011 bd0->buffer_addr = sdma->context_phys; in sdma_load_context()
1012 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; in sdma_load_context()
1015 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_context()
1028 struct sdma_engine *sdma = sdmac->sdma; in sdma_disable_channel()
1029 int channel = sdmac->channel; in sdma_disable_channel()
1031 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
1032 sdmac->status = DMA_ERROR; in sdma_disable_channel()
1051 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_channel_terminate_work()
1052 vchan_get_all_descriptors(&sdmac->vc, &head); in sdma_channel_terminate_work()
1053 sdmac->desc = NULL; in sdma_channel_terminate_work()
1054 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_channel_terminate_work()
1055 vchan_dma_desc_free_list(&sdmac->vc, &head); in sdma_channel_terminate_work()
1064 if (sdmac->desc) in sdma_disable_channel_async()
1065 schedule_work(&sdmac->terminate_worker); in sdma_disable_channel_async()
1074 vchan_synchronize(&sdmac->vc); in sdma_channel_synchronize()
1076 flush_work(&sdmac->terminate_worker); in sdma_channel_synchronize()
1081 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_watermarklevel_for_p2p()
1083 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; in sdma_set_watermarklevel_for_p2p()
1084 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; in sdma_set_watermarklevel_for_p2p()
1086 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1087 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); in sdma_set_watermarklevel_for_p2p()
1089 if (sdmac->event_id0 > 31) in sdma_set_watermarklevel_for_p2p()
1090 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; in sdma_set_watermarklevel_for_p2p()
1092 if (sdmac->event_id1 > 31) in sdma_set_watermarklevel_for_p2p()
1093 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; in sdma_set_watermarklevel_for_p2p()
1101 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | in sdma_set_watermarklevel_for_p2p()
1103 sdmac->watermark_level |= hwml; in sdma_set_watermarklevel_for_p2p()
1104 sdmac->watermark_level |= lwml << 16; in sdma_set_watermarklevel_for_p2p()
1105 swap(sdmac->event_mask[0], sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1108 if (sdmac->per_address2 >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1109 sdmac->per_address2 <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1110 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; in sdma_set_watermarklevel_for_p2p()
1112 if (sdmac->per_address >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1113 sdmac->per_address <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1114 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; in sdma_set_watermarklevel_for_p2p()
1116 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; in sdma_set_watermarklevel_for_p2p()
1126 sdmac->event_mask[0] = 0; in sdma_config_channel()
1127 sdmac->event_mask[1] = 0; in sdma_config_channel()
1128 sdmac->shp_addr = 0; in sdma_config_channel()
1129 sdmac->per_addr = 0; in sdma_config_channel()
1131 switch (sdmac->peripheral_type) { in sdma_config_channel()
1143 sdma_get_pc(sdmac, sdmac->peripheral_type); in sdma_config_channel()
1145 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && in sdma_config_channel()
1146 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { in sdma_config_channel()
1148 if (sdmac->event_id1) { in sdma_config_channel()
1149 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || in sdma_config_channel()
1150 sdmac->peripheral_type == IMX_DMATYPE_ASRC) in sdma_config_channel()
1153 __set_bit(sdmac->event_id0, sdmac->event_mask); in sdma_config_channel()
1156 sdmac->shp_addr = sdmac->per_address; in sdma_config_channel()
1157 sdmac->per_addr = sdmac->per_address2; in sdma_config_channel()
1159 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ in sdma_config_channel()
1170 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_channel_priority()
1171 int channel = sdmac->channel; in sdma_set_channel_priority()
1175 return -EINVAL; in sdma_set_channel_priority()
1178 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
1185 int ret = -EBUSY; in sdma_request_channel0()
1187 sdma->bd0 = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdma->bd0_phys, in sdma_request_channel0()
1189 if (!sdma->bd0) { in sdma_request_channel0()
1190 ret = -ENOMEM; in sdma_request_channel0()
1194 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1195 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1197 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); in sdma_request_channel0()
1207 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_alloc_bd()
1210 desc->bd = dma_zalloc_coherent(NULL, bd_size, &desc->bd_phys, in sdma_alloc_bd()
1212 if (!desc->bd) { in sdma_alloc_bd()
1213 ret = -ENOMEM; in sdma_alloc_bd()
1222 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_free_bd()
1224 dma_free_coherent(NULL, bd_size, desc->bd, desc->bd_phys); in sdma_free_bd()
1238 struct imx_dma_data *data = chan->private; in sdma_alloc_chan_resources()
1243 * MEMCPY may never setup chan->private by filter function such as in sdma_alloc_chan_resources()
1245 * Please note in any other slave case, you have to setup chan->private in sdma_alloc_chan_resources()
1252 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); in sdma_alloc_chan_resources()
1262 switch (data->priority) { in sdma_alloc_chan_resources()
1275 sdmac->peripheral_type = data->peripheral_type; in sdma_alloc_chan_resources()
1276 sdmac->event_id0 = data->dma_request; in sdma_alloc_chan_resources()
1277 sdmac->event_id1 = data->dma_request2; in sdma_alloc_chan_resources()
1279 ret = clk_enable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1282 ret = clk_enable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1293 clk_disable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1295 clk_disable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1302 struct sdma_engine *sdma = sdmac->sdma; in sdma_free_chan_resources()
1308 if (sdmac->event_id0) in sdma_free_chan_resources()
1309 sdma_event_disable(sdmac, sdmac->event_id0); in sdma_free_chan_resources()
1310 if (sdmac->event_id1) in sdma_free_chan_resources()
1311 sdma_event_disable(sdmac, sdmac->event_id1); in sdma_free_chan_resources()
1313 sdmac->event_id0 = 0; in sdma_free_chan_resources()
1314 sdmac->event_id1 = 0; in sdma_free_chan_resources()
1318 clk_disable(sdma->clk_ipg); in sdma_free_chan_resources()
1319 clk_disable(sdma->clk_ahb); in sdma_free_chan_resources()
1331 sdmac->status = DMA_IN_PROGRESS; in sdma_transfer_init()
1332 sdmac->direction = direction; in sdma_transfer_init()
1333 sdmac->flags = 0; in sdma_transfer_init()
1335 desc->chn_count = 0; in sdma_transfer_init()
1336 desc->chn_real_count = 0; in sdma_transfer_init()
1337 desc->buf_tail = 0; in sdma_transfer_init()
1338 desc->buf_ptail = 0; in sdma_transfer_init()
1339 desc->sdmac = sdmac; in sdma_transfer_init()
1340 desc->num_bd = bds; in sdma_transfer_init()
1365 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_memcpy()
1366 int channel = sdmac->channel; in sdma_prep_memcpy()
1375 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", in sdma_prep_memcpy()
1385 bd = &desc->bd[i]; in sdma_prep_memcpy()
1386 bd->buffer_addr = dma_src; in sdma_prep_memcpy()
1387 bd->ext_buffer_addr = dma_dst; in sdma_prep_memcpy()
1388 bd->mode.count = count; in sdma_prep_memcpy()
1389 desc->chn_count += count; in sdma_prep_memcpy()
1390 bd->mode.command = 0; in sdma_prep_memcpy()
1394 len -= count; in sdma_prep_memcpy()
1405 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", in sdma_prep_memcpy()
1406 i, count, bd->buffer_addr, in sdma_prep_memcpy()
1410 bd->mode.status = param; in sdma_prep_memcpy()
1413 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_memcpy()
1422 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_slave_sg()
1424 int channel = sdmac->channel; in sdma_prep_slave_sg()
1428 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_slave_sg()
1434 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", in sdma_prep_slave_sg()
1438 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_slave_sg()
1441 bd->buffer_addr = sg->dma_address; in sdma_prep_slave_sg()
1446 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", in sdma_prep_slave_sg()
1451 bd->mode.count = count; in sdma_prep_slave_sg()
1452 desc->chn_count += count; in sdma_prep_slave_sg()
1454 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_slave_sg()
1457 switch (sdmac->word_size) { in sdma_prep_slave_sg()
1459 bd->mode.command = 0; in sdma_prep_slave_sg()
1460 if (count & 3 || sg->dma_address & 3) in sdma_prep_slave_sg()
1464 bd->mode.command = 2; in sdma_prep_slave_sg()
1465 if (count & 1 || sg->dma_address & 1) in sdma_prep_slave_sg()
1469 bd->mode.command = 1; in sdma_prep_slave_sg()
1483 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", in sdma_prep_slave_sg()
1484 i, count, (u64)sg->dma_address, in sdma_prep_slave_sg()
1488 bd->mode.status = param; in sdma_prep_slave_sg()
1491 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_slave_sg()
1496 sdmac->status = DMA_ERROR; in sdma_prep_slave_sg()
1506 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_dma_cyclic()
1508 int channel = sdmac->channel; in sdma_prep_dma_cyclic()
1512 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); in sdma_prep_dma_cyclic()
1514 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_dma_cyclic()
1520 desc->period_len = period_len; in sdma_prep_dma_cyclic()
1522 sdmac->flags |= IMX_DMA_SG_LOOP; in sdma_prep_dma_cyclic()
1525 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", in sdma_prep_dma_cyclic()
1531 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_dma_cyclic()
1534 bd->buffer_addr = dma_addr; in sdma_prep_dma_cyclic()
1536 bd->mode.count = period_len; in sdma_prep_dma_cyclic()
1538 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1540 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1541 bd->mode.command = 0; in sdma_prep_dma_cyclic()
1543 bd->mode.command = sdmac->word_size; in sdma_prep_dma_cyclic()
1549 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", in sdma_prep_dma_cyclic()
1554 bd->mode.status = param; in sdma_prep_dma_cyclic()
1562 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_dma_cyclic()
1567 sdmac->status = DMA_ERROR; in sdma_prep_dma_cyclic()
1578 sdmac->per_address = dmaengine_cfg->src_addr; in sdma_config_write()
1579 sdmac->watermark_level = dmaengine_cfg->src_maxburst * in sdma_config_write()
1580 dmaengine_cfg->src_addr_width; in sdma_config_write()
1581 sdmac->word_size = dmaengine_cfg->src_addr_width; in sdma_config_write()
1583 sdmac->per_address2 = dmaengine_cfg->src_addr; in sdma_config_write()
1584 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1585 sdmac->watermark_level = dmaengine_cfg->src_maxburst & in sdma_config_write()
1587 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & in sdma_config_write()
1589 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1591 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1592 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * in sdma_config_write()
1593 dmaengine_cfg->dst_addr_width; in sdma_config_write()
1594 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1596 sdmac->direction = direction; in sdma_config_write()
1605 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); in sdma_config()
1608 if (sdmac->event_id0) { in sdma_config()
1609 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1610 return -EINVAL; in sdma_config()
1611 sdma_event_enable(sdmac, sdmac->event_id0); in sdma_config()
1614 if (sdmac->event_id1) { in sdma_config()
1615 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1616 return -EINVAL; in sdma_config()
1617 sdma_event_enable(sdmac, sdmac->event_id1); in sdma_config()
1638 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_tx_status()
1639 vd = vchan_find_desc(&sdmac->vc, cookie); in sdma_tx_status()
1641 desc = to_sdma_desc(&vd->tx); in sdma_tx_status()
1642 if (sdmac->flags & IMX_DMA_SG_LOOP) in sdma_tx_status()
1643 residue = (desc->num_bd - desc->buf_ptail) * in sdma_tx_status()
1644 desc->period_len - desc->chn_real_count; in sdma_tx_status()
1646 residue = desc->chn_count - desc->chn_real_count; in sdma_tx_status()
1647 } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) { in sdma_tx_status()
1648 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count; in sdma_tx_status()
1652 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_tx_status()
1654 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, in sdma_tx_status()
1657 return sdmac->status; in sdma_tx_status()
1665 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_issue_pending()
1666 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) in sdma_issue_pending()
1668 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_issue_pending()
1680 s32 *saddr_arr = (u32 *)sdma->script_addrs; in sdma_add_scripts()
1684 if (!sdma->script_number) in sdma_add_scripts()
1685 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_add_scripts()
1687 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) in sdma_add_scripts()
1689 dev_err(sdma->dev, in sdma_add_scripts()
1691 sdma->script_number); in sdma_add_scripts()
1695 for (i = 0; i < sdma->script_number; i++) in sdma_add_scripts()
1708 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); in sdma_load_firmware()
1713 if (fw->size < sizeof(*header)) in sdma_load_firmware()
1716 header = (struct sdma_firmware_header *)fw->data; in sdma_load_firmware()
1718 if (header->magic != SDMA_FIRMWARE_MAGIC) in sdma_load_firmware()
1720 if (header->ram_code_start + header->ram_code_size > fw->size) in sdma_load_firmware()
1722 switch (header->version_major) { in sdma_load_firmware()
1724 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_load_firmware()
1727 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; in sdma_load_firmware()
1730 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; in sdma_load_firmware()
1733 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; in sdma_load_firmware()
1736 dev_err(sdma->dev, "unknown firmware version\n"); in sdma_load_firmware()
1740 addr = (void *)header + header->script_addrs_start; in sdma_load_firmware()
1741 ram_code = (void *)header + header->ram_code_start; in sdma_load_firmware()
1743 clk_enable(sdma->clk_ipg); in sdma_load_firmware()
1744 clk_enable(sdma->clk_ahb); in sdma_load_firmware()
1747 header->ram_code_size, in sdma_load_firmware()
1748 addr->ram_code_start_addr); in sdma_load_firmware()
1749 clk_disable(sdma->clk_ipg); in sdma_load_firmware()
1750 clk_disable(sdma->clk_ahb); in sdma_load_firmware()
1754 dev_info(sdma->dev, "loaded firmware %d.%d\n", in sdma_load_firmware()
1755 header->version_major, in sdma_load_firmware()
1756 header->version_minor); in sdma_load_firmware()
1766 struct device_node *np = sdma->dev->of_node; in sdma_event_remap()
1770 char propname[] = "fsl,sdma-event-remap"; in sdma_event_remap()
1778 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; in sdma_event_remap()
1780 dev_dbg(sdma->dev, "no event needs to be remapped\n"); in sdma_event_remap()
1783 dev_err(sdma->dev, "the property %s must modulo %d\n", in sdma_event_remap()
1785 ret = -EINVAL; in sdma_event_remap()
1791 dev_err(sdma->dev, "failed to get gpr regmap\n"); in sdma_event_remap()
1799 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1806 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1813 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1834 FW_ACTION_HOTPLUG, fw_name, sdma->dev, in sdma_get_firmware()
1845 ret = clk_enable(sdma->clk_ipg); in sdma_init()
1848 ret = clk_enable(sdma->clk_ahb); in sdma_init()
1853 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); in sdma_init()
1855 sdma->channel_control = dma_alloc_coherent(NULL, in sdma_init()
1860 if (!sdma->channel_control) { in sdma_init()
1861 ret = -ENOMEM; in sdma_init()
1865 sdma->context = (void *)sdma->channel_control + in sdma_init()
1867 sdma->context_phys = ccb_phys + in sdma_init()
1870 /* Zero-out the CCB structures array just allocated */ in sdma_init()
1871 memset(sdma->channel_control, 0, in sdma_init()
1875 for (i = 0; i < sdma->drvdata->num_events; i++) in sdma_init()
1876 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); in sdma_init()
1880 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); in sdma_init()
1886 sdma_config_ownership(&sdma->channel[0], false, true, false); in sdma_init()
1889 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); in sdma_init()
1893 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); in sdma_init()
1895 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); in sdma_init()
1898 sdma_set_channel_priority(&sdma->channel[0], 7); in sdma_init()
1900 clk_disable(sdma->clk_ipg); in sdma_init()
1901 clk_disable(sdma->clk_ahb); in sdma_init()
1906 clk_disable(sdma->clk_ahb); in sdma_init()
1908 clk_disable(sdma->clk_ipg); in sdma_init()
1909 dev_err(sdma->dev, "initialisation failed with %d\n", ret); in sdma_init()
1921 sdmac->data = *data; in sdma_filter_fn()
1922 chan->private = &sdmac->data; in sdma_filter_fn()
1930 struct sdma_engine *sdma = ofdma->of_dma_data; in sdma_xlate()
1931 dma_cap_mask_t mask = sdma->dma_device.cap_mask; in sdma_xlate()
1934 if (dma_spec->args_count != 3) in sdma_xlate()
1937 data.dma_request = dma_spec->args[0]; in sdma_xlate()
1938 data.peripheral_type = dma_spec->args[1]; in sdma_xlate()
1939 data.priority = dma_spec->args[2]; in sdma_xlate()
1943 * chan->private will point to the imx_dma_data, and in in sdma_xlate()
1945 * be set to sdmac->event_id1. in sdma_xlate()
1955 of_match_device(sdma_dt_ids, &pdev->dev); in sdma_probe()
1956 struct device_node *np = pdev->dev.of_node; in sdma_probe()
1963 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); in sdma_probe()
1970 drvdata = of_id->data; in sdma_probe()
1971 else if (pdev->id_entry) in sdma_probe()
1972 drvdata = (void *)pdev->id_entry->driver_data; in sdma_probe()
1975 dev_err(&pdev->dev, "unable to find driver data\n"); in sdma_probe()
1976 return -EINVAL; in sdma_probe()
1979 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in sdma_probe()
1983 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); in sdma_probe()
1985 return -ENOMEM; in sdma_probe()
1987 spin_lock_init(&sdma->channel_0_lock); in sdma_probe()
1989 sdma->dev = &pdev->dev; in sdma_probe()
1990 sdma->drvdata = drvdata; in sdma_probe()
1997 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); in sdma_probe()
1998 if (IS_ERR(sdma->regs)) in sdma_probe()
1999 return PTR_ERR(sdma->regs); in sdma_probe()
2001 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdma_probe()
2002 if (IS_ERR(sdma->clk_ipg)) in sdma_probe()
2003 return PTR_ERR(sdma->clk_ipg); in sdma_probe()
2005 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdma_probe()
2006 if (IS_ERR(sdma->clk_ahb)) in sdma_probe()
2007 return PTR_ERR(sdma->clk_ahb); in sdma_probe()
2009 ret = clk_prepare(sdma->clk_ipg); in sdma_probe()
2013 ret = clk_prepare(sdma->clk_ahb); in sdma_probe()
2017 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", in sdma_probe()
2022 sdma->irq = irq; in sdma_probe()
2024 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); in sdma_probe()
2025 if (!sdma->script_addrs) { in sdma_probe()
2026 ret = -ENOMEM; in sdma_probe()
2031 saddr_arr = (s32 *)sdma->script_addrs; in sdma_probe()
2033 saddr_arr[i] = -EINVAL; in sdma_probe()
2035 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); in sdma_probe()
2036 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); in sdma_probe()
2037 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); in sdma_probe()
2039 INIT_LIST_HEAD(&sdma->dma_device.channels); in sdma_probe()
2042 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_probe()
2044 sdmac->sdma = sdma; in sdma_probe()
2046 sdmac->channel = i; in sdma_probe()
2047 sdmac->vc.desc_free = sdma_desc_free; in sdma_probe()
2048 INIT_WORK(&sdmac->terminate_worker, in sdma_probe()
2056 vchan_init(&sdmac->vc, &sdma->dma_device); in sdma_probe()
2067 if (sdma->drvdata->script_addrs) in sdma_probe()
2068 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); in sdma_probe()
2069 if (pdata && pdata->script_addrs) in sdma_probe()
2070 sdma_add_scripts(sdma, pdata->script_addrs); in sdma_probe()
2072 sdma->dma_device.dev = &pdev->dev; in sdma_probe()
2074 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; in sdma_probe()
2075 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; in sdma_probe()
2076 sdma->dma_device.device_tx_status = sdma_tx_status; in sdma_probe()
2077 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; in sdma_probe()
2078 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; in sdma_probe()
2079 sdma->dma_device.device_config = sdma_config; in sdma_probe()
2080 sdma->dma_device.device_terminate_all = sdma_disable_channel_async; in sdma_probe()
2081 sdma->dma_device.device_synchronize = sdma_channel_synchronize; in sdma_probe()
2082 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2083 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2084 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; in sdma_probe()
2085 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in sdma_probe()
2086 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; in sdma_probe()
2087 sdma->dma_device.device_issue_pending = sdma_issue_pending; in sdma_probe()
2088 sdma->dma_device.dev->dma_parms = &sdma->dma_parms; in sdma_probe()
2089 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); in sdma_probe()
2093 ret = dma_async_device_register(&sdma->dma_device); in sdma_probe()
2095 dev_err(&pdev->dev, "unable to register\n"); in sdma_probe()
2102 dev_err(&pdev->dev, "failed to register controller\n"); in sdma_probe()
2106 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); in sdma_probe()
2109 sdma->spba_start_addr = spba_res.start; in sdma_probe()
2110 sdma->spba_end_addr = spba_res.end; in sdma_probe()
2122 ret = sdma_get_firmware(sdma, pdata->fw_name); in sdma_probe()
2124 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); in sdma_probe()
2131 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", in sdma_probe()
2134 dev_warn(&pdev->dev, "failed to get firmware name\n"); in sdma_probe()
2138 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); in sdma_probe()
2145 dma_async_device_unregister(&sdma->dma_device); in sdma_probe()
2147 kfree(sdma->script_addrs); in sdma_probe()
2149 clk_unprepare(sdma->clk_ahb); in sdma_probe()
2151 clk_unprepare(sdma->clk_ipg); in sdma_probe()
2160 devm_free_irq(&pdev->dev, sdma->irq, sdma); in sdma_remove()
2161 dma_async_device_unregister(&sdma->dma_device); in sdma_remove()
2162 kfree(sdma->script_addrs); in sdma_remove()
2163 clk_unprepare(sdma->clk_ahb); in sdma_remove()
2164 clk_unprepare(sdma->clk_ipg); in sdma_remove()
2167 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_remove()
2169 tasklet_kill(&sdmac->vc.task); in sdma_remove()
2170 sdma_free_chan_resources(&sdmac->vc.chan); in sdma_remove()
2179 .name = "imx-sdma",
2192 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2195 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");