Lines Matching +full:dma +full:- +full:maxburst
14 #include <linux/dma-mapping.h>
25 #include <linux/dma/pxa-dma.h>
28 #include "virt-dma.h"
39 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
41 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
42 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
67 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
74 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
77 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
97 struct pxad_desc_hw *hw_desc[]; /* DMA coherent descriptors */
118 /* protected by vc->lock */
150 readl_relaxed((phy)->base + _reg((phy)->idx))
154 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \
155 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
162 writel((val), (phy)->base + _reg((phy)->idx)); \
163 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
169 writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \
170 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
194 struct pxad_phy *phy = s->private; in dbg_show_requester_chan()
198 seq_printf(s, "DMA channel %d requester :\n", phy->idx); in dbg_show_requester_chan()
200 drcmr = readl_relaxed(phy->base + pxad_drcmr(i)); in dbg_show_requester_chan()
201 if ((drcmr & DRCMR_CHLNUM) == phy->idx) in dbg_show_requester_chan()
225 struct pxad_phy *phy = s->private; in dbg_show_descriptors()
233 seq_printf(s, "DMA channel %d descriptors :\n", phy->idx); in dbg_show_descriptors()
237 dcmd = desc->dcmd; in dbg_show_descriptors()
243 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr); in dbg_show_descriptors()
244 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr); in dbg_show_descriptors()
245 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr); in dbg_show_descriptors()
253 phys_desc = desc->ddadr; in dbg_show_descriptors()
268 struct pxad_phy *phy = s->private; in dbg_show_chan_state()
280 seq_printf(s, "DMA channel %d\n", phy->idx); in dbg_show_chan_state()
282 str_prio[(phy->idx & 0xf) / 4]); in dbg_show_chan_state()
284 _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ? in dbg_show_chan_state()
311 struct pxad_device *pdev = s->private; in dbg_show_state()
314 seq_puts(s, "DMA engine status\n"); in dbg_show_state()
315 seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans); in dbg_show_state()
323 return single_open(file, dbg_show_##name, inode->i_private); \
347 dt = (void *)&pdev->phys[ch]; in pxad_dbg_alloc_chan()
373 pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL); in pxad_init_debugfs()
374 if (IS_ERR(pdev->dbgfs_root) || !pdev->dbgfs_root) in pxad_init_debugfs()
377 pdev->dbgfs_state = debugfs_create_file("state", 0400, pdev->dbgfs_root, in pxad_init_debugfs()
379 if (!pdev->dbgfs_state) in pxad_init_debugfs()
382 pdev->dbgfs_chan = in pxad_init_debugfs()
383 kmalloc_array(pdev->nr_chans, sizeof(*pdev->dbgfs_state), in pxad_init_debugfs()
385 if (!pdev->dbgfs_chan) in pxad_init_debugfs()
388 chandir = debugfs_create_dir("channels", pdev->dbgfs_root); in pxad_init_debugfs()
392 for (i = 0; i < pdev->nr_chans; i++) { in pxad_init_debugfs()
393 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir); in pxad_init_debugfs()
394 if (!pdev->dbgfs_chan[i]) in pxad_init_debugfs()
401 kfree(pdev->dbgfs_chan); in pxad_init_debugfs()
404 debugfs_remove_recursive(pdev->dbgfs_root); in pxad_init_debugfs()
411 debugfs_remove_recursive(pdev->dbgfs_root); in pxad_cleanup_debugfs()
421 struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device); in lookup_phy()
426 * dma channel priorities in lookup_phy()
427 * ch 0 - 3, 16 - 19 <--> (0) in lookup_phy()
428 * ch 4 - 7, 20 - 23 <--> (1) in lookup_phy()
429 * ch 8 - 11, 24 - 27 <--> (2) in lookup_phy()
430 * ch 12 - 15, 28 - 31 <--> (3) in lookup_phy()
433 spin_lock_irqsave(&pdev->phy_lock, flags); in lookup_phy()
434 for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) { in lookup_phy()
435 for (i = 0; i < pdev->nr_chans; i++) { in lookup_phy()
438 phy = &pdev->phys[i]; in lookup_phy()
439 if (!phy->vchan) { in lookup_phy()
440 phy->vchan = pchan; in lookup_phy()
448 spin_unlock_irqrestore(&pdev->phy_lock, flags); in lookup_phy()
449 dev_dbg(&pchan->vc.chan.dev->device, in lookup_phy()
451 found ? found->idx : -1); in lookup_phy()
458 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_free_phy()
462 dev_dbg(&chan->vc.chan.dev->device, in pxad_free_phy()
464 if (!chan->phy) in pxad_free_phy()
468 if (chan->drcmr <= pdev->nr_requestors) { in pxad_free_phy()
469 reg = pxad_drcmr(chan->drcmr); in pxad_free_phy()
470 writel_relaxed(0, chan->phy->base + reg); in pxad_free_phy()
473 spin_lock_irqsave(&pdev->phy_lock, flags); in pxad_free_phy()
474 chan->phy->vchan = NULL; in pxad_free_phy()
475 chan->phy = NULL; in pxad_free_phy()
476 spin_unlock_irqrestore(&pdev->phy_lock, flags); in pxad_free_phy()
482 struct pxad_phy *phy = chan->phy; in is_chan_running()
494 BUG_ON(!chan->phy); in is_running_chan_misaligned()
495 dalgn = phy_readl_relaxed(chan->phy, DALGN); in is_running_chan_misaligned()
496 return dalgn & (BIT(chan->phy->idx)); in is_running_chan_misaligned()
504 if (!phy->vchan) in phy_enable()
507 dev_dbg(&phy->vchan->vc.chan.dev->device, in phy_enable()
509 phy, phy->idx, misaligned); in phy_enable()
511 pdev = to_pxad_dev(phy->vchan->vc.chan.device); in phy_enable()
512 if (phy->vchan->drcmr <= pdev->nr_requestors) { in phy_enable()
513 reg = pxad_drcmr(phy->vchan->drcmr); in phy_enable()
514 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); in phy_enable()
519 dalgn |= BIT(phy->idx); in phy_enable()
521 dalgn &= ~BIT(phy->idx); in phy_enable()
536 dev_dbg(&phy->vchan->vc.chan.dev->device, in phy_disable()
537 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx); in phy_disable()
544 dev_dbg(&chan->vc.chan.dev->device, in pxad_launch_chan()
546 if (!chan->phy) { in pxad_launch_chan()
547 chan->phy = lookup_phy(chan); in pxad_launch_chan()
548 if (!chan->phy) { in pxad_launch_chan()
549 dev_dbg(&chan->vc.chan.dev->device, in pxad_launch_chan()
550 "%s(): no free dma channel\n", __func__); in pxad_launch_chan()
554 chan->bus_error = 0; in pxad_launch_chan()
557 * Program the descriptor's address into the DMA controller, in pxad_launch_chan()
558 * then start the DMA transaction in pxad_launch_chan()
560 phy_writel(chan->phy, desc->first, DDADR); in pxad_launch_chan()
561 phy_enable(chan->phy, chan->misaligned); in pxad_launch_chan()
562 wake_up(&chan->wq_state); in pxad_launch_chan()
569 sw_desc->hw_desc[sw_desc->nb_desc - 1]; in set_updater_desc()
570 dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr; in set_updater_desc() local
572 updater->ddadr = DDADR_STOP; in set_updater_desc()
573 updater->dsadr = dma; in set_updater_desc()
574 updater->dtadr = dma + 8; in set_updater_desc()
575 updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 | in set_updater_desc()
578 updater->dcmd |= PXA_DCMD_ENDIRQEN; in set_updater_desc()
579 if (sw_desc->cyclic) in set_updater_desc()
580 sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first; in set_updater_desc()
587 sw_desc->hw_desc[sw_desc->nb_desc - 1]; in is_desc_completed()
589 return updater->dtadr != (updater->dsadr + 8); in is_desc_completed()
599 dma_to_chain = desc2->first; in pxad_desc_chain()
600 desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain; in pxad_desc_chain()
607 struct pxad_chan *chan = to_pxad_chan(&vc->chan); in pxad_try_hotchain()
617 BUG_ON(list_empty(&vc->desc_issued)); in pxad_try_hotchain()
620 to_pxad_sw_desc(vd)->misaligned) in pxad_try_hotchain()
623 vd_last_issued = list_entry(vc->desc_issued.prev, in pxad_try_hotchain()
636 u32 dint = readl(phy->base + DINT); in clear_chan_irq()
638 if (!(dint & BIT(phy->idx))) in clear_chan_irq()
644 if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan)) in clear_chan_irq()
645 dev_warn(&phy->vchan->vc.chan.dev->device, in clear_chan_irq()
647 __func__, &phy->vchan); in clear_chan_irq()
655 struct pxad_chan *chan = phy->vchan; in pxad_chan_handler()
668 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_chan_handler()
669 list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) { in pxad_chan_handler()
671 dev_dbg(&chan->vc.chan.dev->device, in pxad_chan_handler()
673 __func__, vd, vd->tx.cookie, vd_completed, in pxad_chan_handler()
675 last_started = vd->tx.cookie; in pxad_chan_handler()
676 if (to_pxad_sw_desc(vd)->cyclic) { in pxad_chan_handler()
681 list_del(&vd->node); in pxad_chan_handler()
689 chan->bus_error = last_started; in pxad_chan_handler()
693 if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) { in pxad_chan_handler()
694 dev_dbg(&chan->vc.chan.dev->device, in pxad_chan_handler()
697 list_empty(&chan->vc.desc_submitted), in pxad_chan_handler()
698 list_empty(&chan->vc.desc_issued)); in pxad_chan_handler()
701 if (list_empty(&chan->vc.desc_issued)) { in pxad_chan_handler()
702 chan->misaligned = in pxad_chan_handler()
703 !list_empty(&chan->vc.desc_submitted); in pxad_chan_handler()
705 vd = list_first_entry(&chan->vc.desc_issued, in pxad_chan_handler()
710 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_chan_handler()
711 wake_up(&chan->wq_state); in pxad_chan_handler()
720 u32 dint = readl(pdev->base + DINT); in pxad_int_handler()
725 dint &= (dint - 1); in pxad_int_handler()
726 phy = &pdev->phys[i]; in pxad_int_handler()
737 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_alloc_chan_resources()
739 if (chan->desc_pool) in pxad_alloc_chan_resources()
742 chan->desc_pool = dma_pool_create(dma_chan_name(dchan), in pxad_alloc_chan_resources()
743 pdev->slave.dev, in pxad_alloc_chan_resources()
747 if (!chan->desc_pool) { in pxad_alloc_chan_resources()
748 dev_err(&chan->vc.chan.dev->device, in pxad_alloc_chan_resources()
751 return -ENOMEM; in pxad_alloc_chan_resources()
761 vchan_free_chan_resources(&chan->vc); in pxad_free_chan_resources()
762 dma_pool_destroy(chan->desc_pool); in pxad_free_chan_resources()
763 chan->desc_pool = NULL; in pxad_free_chan_resources()
765 chan->drcmr = U32_MAX; in pxad_free_chan_resources()
766 chan->prio = PXAD_PRIO_LOWEST; in pxad_free_chan_resources()
772 dma_addr_t dma; in pxad_free_desc() local
775 BUG_ON(sw_desc->nb_desc == 0); in pxad_free_desc()
776 for (i = sw_desc->nb_desc - 1; i >= 0; i--) { in pxad_free_desc()
778 dma = sw_desc->hw_desc[i - 1]->ddadr; in pxad_free_desc()
780 dma = sw_desc->first; in pxad_free_desc()
781 dma_pool_free(sw_desc->desc_pool, in pxad_free_desc()
782 sw_desc->hw_desc[i], dma); in pxad_free_desc()
784 sw_desc->nb_desc = 0; in pxad_free_desc()
792 dma_addr_t dma; in pxad_alloc_desc() local
800 sw_desc->desc_pool = chan->desc_pool; in pxad_alloc_desc()
803 sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool, in pxad_alloc_desc()
804 GFP_NOWAIT, &dma); in pxad_alloc_desc()
805 if (!sw_desc->hw_desc[i]) { in pxad_alloc_desc()
806 dev_err(&chan->vc.chan.dev->device, in pxad_alloc_desc()
808 __func__, i, sw_desc->desc_pool); in pxad_alloc_desc()
813 sw_desc->first = dma; in pxad_alloc_desc()
815 sw_desc->hw_desc[i - 1]->ddadr = dma; in pxad_alloc_desc()
816 sw_desc->nb_desc++; in pxad_alloc_desc()
821 pxad_free_desc(&sw_desc->vd); in pxad_alloc_desc()
827 struct virt_dma_chan *vc = to_virt_chan(tx->chan); in pxad_tx_submit()
828 struct pxad_chan *chan = to_pxad_chan(&vc->chan); in pxad_tx_submit()
834 set_updater_desc(to_pxad_sw_desc(vd), tx->flags); in pxad_tx_submit()
836 spin_lock_irqsave(&vc->lock, flags); in pxad_tx_submit()
839 if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) { in pxad_tx_submit()
840 list_move_tail(&vd->node, &vc->desc_issued); in pxad_tx_submit()
841 dev_dbg(&chan->vc.chan.dev->device, in pxad_tx_submit()
850 if (!list_empty(&vc->desc_submitted)) { in pxad_tx_submit()
851 vd_chained = list_entry(vc->desc_submitted.prev, in pxad_tx_submit()
859 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned) in pxad_tx_submit()
864 dev_dbg(&chan->vc.chan.dev->device, in pxad_tx_submit()
867 list_move_tail(&vd->node, &vc->desc_submitted); in pxad_tx_submit()
868 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned; in pxad_tx_submit()
871 spin_unlock_irqrestore(&vc->lock, flags); in pxad_tx_submit()
881 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_issue_pending()
882 if (list_empty(&chan->vc.desc_submitted)) in pxad_issue_pending()
885 vd_first = list_first_entry(&chan->vc.desc_submitted, in pxad_issue_pending()
887 dev_dbg(&chan->vc.chan.dev->device, in pxad_issue_pending()
888 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie); in pxad_issue_pending()
890 vchan_issue_pending(&chan->vc); in pxad_issue_pending()
891 if (!pxad_try_hotchain(&chan->vc, vd_first)) in pxad_issue_pending()
894 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_issue_pending()
904 INIT_LIST_HEAD(&vd->node); in pxad_tx_prep()
906 tx->tx_submit = pxad_tx_submit; in pxad_tx_prep()
907 dev_dbg(&chan->vc.chan.dev->device, in pxad_tx_prep()
909 vc, vd, vd->tx.cookie, in pxad_tx_prep()
919 u32 maxburst = 0, dev_addr = 0; in pxad_get_config() local
921 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_get_config()
925 maxburst = chan->cfg.src_maxburst; in pxad_get_config()
926 width = chan->cfg.src_addr_width; in pxad_get_config()
927 dev_addr = chan->cfg.src_addr; in pxad_get_config()
930 if (chan->drcmr <= pdev->nr_requestors) in pxad_get_config()
934 maxburst = chan->cfg.dst_maxburst; in pxad_get_config()
935 width = chan->cfg.dst_addr_width; in pxad_get_config()
936 dev_addr = chan->cfg.dst_addr; in pxad_get_config()
939 if (chan->drcmr <= pdev->nr_requestors) in pxad_get_config()
946 dev_dbg(&chan->vc.chan.dev->device, in pxad_get_config()
947 "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d\n", in pxad_get_config()
948 __func__, dev_addr, maxburst, width, dir); in pxad_get_config()
957 if (maxburst == 8) in pxad_get_config()
959 else if (maxburst == 16) in pxad_get_config()
961 else if (maxburst == 32) in pxad_get_config()
968 if (chan->cfg.slave_id) in pxad_get_config()
969 chan->drcmr = chan->cfg.slave_id; in pxad_get_config()
987 dev_dbg(&chan->vc.chan.dev->device, in pxad_prep_memcpy()
997 sw_desc->len = len; in pxad_prep_memcpy()
1001 sw_desc->misaligned = true; in pxad_prep_memcpy()
1005 hw_desc = sw_desc->hw_desc[i++]; in pxad_prep_memcpy()
1007 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy); in pxad_prep_memcpy()
1008 hw_desc->dsadr = dma_src; in pxad_prep_memcpy()
1009 hw_desc->dtadr = dma_dst; in pxad_prep_memcpy()
1010 len -= copy; in pxad_prep_memcpy()
1016 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); in pxad_prep_memcpy()
1028 dma_addr_t dma; in pxad_prep_slave_sg() local
1036 dev_dbg(&chan->vc.chan.dev->device, in pxad_prep_slave_sg()
1046 dma = sg_dma_address(sg); in pxad_prep_slave_sg()
1048 sw_desc->len += avail; in pxad_prep_slave_sg()
1052 if (dma & 0x7) in pxad_prep_slave_sg()
1053 sw_desc->misaligned = true; in pxad_prep_slave_sg()
1055 sw_desc->hw_desc[j]->dcmd = in pxad_prep_slave_sg()
1057 sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma; in pxad_prep_slave_sg()
1058 sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma; in pxad_prep_slave_sg()
1060 dma += len; in pxad_prep_slave_sg()
1061 avail -= len; in pxad_prep_slave_sg()
1066 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); in pxad_prep_slave_sg()
1077 dma_addr_t dma; in pxad_prep_dma_cyclic() local
1084 dev_err(&chan->vc.chan.dev->device, in pxad_prep_dma_cyclic()
1085 "Unsupported direction for cyclic DMA\n"); in pxad_prep_dma_cyclic()
1095 dev_dbg(&chan->vc.chan.dev->device, in pxad_prep_dma_cyclic()
1104 sw_desc->cyclic = true; in pxad_prep_dma_cyclic()
1105 sw_desc->len = len; in pxad_prep_dma_cyclic()
1107 phw_desc = sw_desc->hw_desc; in pxad_prep_dma_cyclic()
1108 dma = buf_addr; in pxad_prep_dma_cyclic()
1110 phw_desc[0]->dsadr = dsadr ? dsadr : dma; in pxad_prep_dma_cyclic()
1111 phw_desc[0]->dtadr = dtadr ? dtadr : dma; in pxad_prep_dma_cyclic()
1112 phw_desc[0]->dcmd = dcmd; in pxad_prep_dma_cyclic()
1114 dma += period_len; in pxad_prep_dma_cyclic()
1115 len -= period_len; in pxad_prep_dma_cyclic()
1119 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); in pxad_prep_dma_cyclic()
1128 return -EINVAL; in pxad_config()
1130 chan->cfg = *cfg; in pxad_config()
1137 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_terminate_all()
1143 dev_dbg(&chan->vc.chan.dev->device, in pxad_terminate_all()
1144 "%s(): vchan %p: terminate all\n", __func__, &chan->vc); in pxad_terminate_all()
1146 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_terminate_all()
1147 vchan_get_all_descriptors(&chan->vc, &head); in pxad_terminate_all()
1150 dev_dbg(&chan->vc.chan.dev->device, in pxad_terminate_all()
1152 vd, vd->tx.cookie, is_desc_completed(vd)); in pxad_terminate_all()
1155 phy = chan->phy; in pxad_terminate_all()
1157 phy_disable(chan->phy); in pxad_terminate_all()
1159 chan->phy = NULL; in pxad_terminate_all()
1160 spin_lock(&pdev->phy_lock); in pxad_terminate_all()
1161 phy->vchan = NULL; in pxad_terminate_all()
1162 spin_unlock(&pdev->phy_lock); in pxad_terminate_all()
1164 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_terminate_all()
1165 vchan_dma_desc_free_list(&chan->vc, &head); in pxad_terminate_all()
1185 if (!chan->phy) in pxad_residue()
1188 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_residue()
1190 vd = vchan_find_desc(&chan->vc, cookie); in pxad_residue()
1195 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) in pxad_residue()
1196 curr = phy_readl_relaxed(chan->phy, DSADR); in pxad_residue()
1198 curr = phy_readl_relaxed(chan->phy, DTADR); in pxad_residue()
1210 for (i = 0; i < sw_desc->nb_desc - 1; i++) { in pxad_residue()
1211 hw_desc = sw_desc->hw_desc[i]; in pxad_residue()
1212 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) in pxad_residue()
1213 start = hw_desc->dsadr; in pxad_residue()
1215 start = hw_desc->dtadr; in pxad_residue()
1216 len = hw_desc->dcmd & PXA_DCMD_LENGTH; in pxad_residue()
1231 residue += end - curr; in pxad_residue()
1236 residue = sw_desc->len; in pxad_residue()
1239 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_residue()
1240 dev_dbg(&chan->vc.chan.dev->device, in pxad_residue()
1253 if (cookie == chan->bus_error) in pxad_tx_status()
1267 wait_event(chan->wq_state, !is_chan_running(chan)); in pxad_synchronize()
1268 vchan_synchronize(&chan->vc); in pxad_synchronize()
1275 list_for_each_entry_safe(c, cn, &dmadev->channels, in pxad_free_channels()
1277 list_del(&c->vc.chan.device_node); in pxad_free_channels()
1278 tasklet_kill(&c->vc.task); in pxad_free_channels()
1287 pxad_free_channels(&pdev->slave); in pxad_remove()
1288 dma_async_device_unregister(&pdev->slave); in pxad_remove()
1303 pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans, in pxad_init_phys()
1304 sizeof(pdev->phys[0]), GFP_KERNEL); in pxad_init_phys()
1305 if (!pdev->phys) in pxad_init_phys()
1306 return -ENOMEM; in pxad_init_phys()
1313 phy = &pdev->phys[i]; in pxad_init_phys()
1314 phy->base = pdev->base; in pxad_init_phys()
1315 phy->idx = i; in pxad_init_phys()
1318 ret = devm_request_irq(&op->dev, irq, in pxad_init_phys()
1320 IRQF_SHARED, "pxa-dma", phy); in pxad_init_phys()
1322 ret = devm_request_irq(&op->dev, irq0, in pxad_init_phys()
1324 IRQF_SHARED, "pxa-dma", pdev); in pxad_init_phys()
1326 dev_err(pdev->slave.dev, in pxad_init_phys()
1337 { .compatible = "marvell,pdma-1.0", },
1345 struct pxad_device *d = ofdma->of_dma_data; in pxad_dma_xlate()
1348 chan = dma_get_any_slave_channel(&d->slave); in pxad_dma_xlate()
1352 to_pxad_chan(chan)->drcmr = dma_spec->args[0]; in pxad_dma_xlate()
1353 to_pxad_chan(chan)->prio = dma_spec->args[1]; in pxad_dma_xlate()
1367 pdev->nr_chans = nr_phy_chans; in pxad_init_dmadev()
1368 pdev->nr_requestors = nr_requestors; in pxad_init_dmadev()
1369 INIT_LIST_HEAD(&pdev->slave.channels); in pxad_init_dmadev()
1370 pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources; in pxad_init_dmadev()
1371 pdev->slave.device_free_chan_resources = pxad_free_chan_resources; in pxad_init_dmadev()
1372 pdev->slave.device_tx_status = pxad_tx_status; in pxad_init_dmadev()
1373 pdev->slave.device_issue_pending = pxad_issue_pending; in pxad_init_dmadev()
1374 pdev->slave.device_config = pxad_config; in pxad_init_dmadev()
1375 pdev->slave.device_synchronize = pxad_synchronize; in pxad_init_dmadev()
1376 pdev->slave.device_terminate_all = pxad_terminate_all; in pxad_init_dmadev()
1378 if (op->dev.coherent_dma_mask) in pxad_init_dmadev()
1379 dma_set_mask(&op->dev, op->dev.coherent_dma_mask); in pxad_init_dmadev()
1381 dma_set_mask(&op->dev, DMA_BIT_MASK(32)); in pxad_init_dmadev()
1388 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL); in pxad_init_dmadev()
1390 return -ENOMEM; in pxad_init_dmadev()
1392 c->drcmr = U32_MAX; in pxad_init_dmadev()
1393 c->prio = PXAD_PRIO_LOWEST; in pxad_init_dmadev()
1394 c->vc.desc_free = pxad_free_desc; in pxad_init_dmadev()
1395 vchan_init(&c->vc, &pdev->slave); in pxad_init_dmadev()
1396 init_waitqueue_head(&c->wq_state); in pxad_init_dmadev()
1399 return dma_async_device_register(&pdev->slave); in pxad_init_dmadev()
1407 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev); in pxad_probe()
1414 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL); in pxad_probe()
1416 return -ENOMEM; in pxad_probe()
1418 spin_lock_init(&pdev->phy_lock); in pxad_probe()
1421 pdev->base = devm_ioremap_resource(&op->dev, iores); in pxad_probe()
1422 if (IS_ERR(pdev->base)) in pxad_probe()
1423 return PTR_ERR(pdev->base); in pxad_probe()
1425 of_id = of_match_device(pxad_dt_ids, &op->dev); in pxad_probe()
1427 of_property_read_u32(op->dev.of_node, "#dma-channels", in pxad_probe()
1429 ret = of_property_read_u32(op->dev.of_node, "#dma-requests", in pxad_probe()
1432 dev_warn(pdev->slave.dev, in pxad_probe()
1433 "#dma-requests set to default 32 as missing in OF: %d", in pxad_probe()
1437 } else if (pdata && pdata->dma_channels) { in pxad_probe()
1438 dma_channels = pdata->dma_channels; in pxad_probe()
1439 nb_requestors = pdata->nb_requestors; in pxad_probe()
1440 slave_map = pdata->slave_map; in pxad_probe()
1441 slave_map_cnt = pdata->slave_map_cnt; in pxad_probe()
1446 dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask); in pxad_probe()
1447 dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask); in pxad_probe()
1448 dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask); in pxad_probe()
1449 dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask); in pxad_probe()
1450 pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy; in pxad_probe()
1451 pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg; in pxad_probe()
1452 pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic; in pxad_probe()
1453 pdev->slave.filter.map = slave_map; in pxad_probe()
1454 pdev->slave.filter.mapcnt = slave_map_cnt; in pxad_probe()
1455 pdev->slave.filter.fn = pxad_filter_fn; in pxad_probe()
1457 pdev->slave.copy_align = PDMA_ALIGNMENT; in pxad_probe()
1458 pdev->slave.src_addr_widths = widths; in pxad_probe()
1459 pdev->slave.dst_addr_widths = widths; in pxad_probe()
1460 pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); in pxad_probe()
1461 pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; in pxad_probe()
1462 pdev->slave.descriptor_reuse = true; in pxad_probe()
1464 pdev->slave.dev = &op->dev; in pxad_probe()
1467 dev_err(pdev->slave.dev, "unable to register\n"); in pxad_probe()
1471 if (op->dev.of_node) { in pxad_probe()
1472 /* Device-tree DMA controller registration */ in pxad_probe()
1473 ret = of_dma_controller_register(op->dev.of_node, in pxad_probe()
1476 dev_err(pdev->slave.dev, in pxad_probe()
1484 dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n", in pxad_probe()
1490 { "pxa-dma", },
1496 .name = "pxa-dma",
1509 if (chan->device->dev->driver != &pxad_driver.driver) in pxad_filter_fn()
1512 c->drcmr = p->drcmr; in pxad_filter_fn()
1513 c->prio = p->prio; in pxad_filter_fn()
1521 MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver");