Lines Matching +full:ahb +full:- +full:addr +full:- +full:masks
5 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
20 * Inspired by stm32-dma.c and dma-jz4780.c
27 #include <linux/dma-mapping.h>
43 #include "virt-dma.h"
46 #define STM32_MDMA_SHIFT(n) (ffs(n) - 1)
297 return container_of(chan->vchan.chan.device, struct stm32_mdma_device, in stm32_mdma_get_dev()
313 return &chan->vchan.chan.dev->device; in chan2dev()
318 return mdma_dev->ddev.dev; in mdma2dev()
323 return readl_relaxed(dmadev->base + reg); in stm32_mdma_read()
328 writel_relaxed(val, dmadev->base + reg); in stm32_mdma_write()
334 void __iomem *addr = dmadev->base + reg; in stm32_mdma_set_bits() local
336 writel_relaxed(readl_relaxed(addr) | mask, addr); in stm32_mdma_set_bits()
342 void __iomem *addr = dmadev->base + reg; in stm32_mdma_clr_bits() local
344 writel_relaxed(readl_relaxed(addr) & ~mask, addr); in stm32_mdma_clr_bits()
358 desc->node[i].hwdesc = in stm32_mdma_alloc_desc()
359 dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, in stm32_mdma_alloc_desc()
360 &desc->node[i].hwdesc_phys); in stm32_mdma_alloc_desc()
361 if (!desc->node[i].hwdesc) in stm32_mdma_alloc_desc()
365 desc->count = count; in stm32_mdma_alloc_desc()
371 while (--i >= 0) in stm32_mdma_alloc_desc()
372 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc, in stm32_mdma_alloc_desc()
373 desc->node[i].hwdesc_phys); in stm32_mdma_alloc_desc()
381 struct stm32_mdma_chan *chan = to_stm32_mdma_chan(vdesc->tx.chan); in stm32_mdma_desc_free()
384 for (i = 0; i < desc->count; i++) in stm32_mdma_desc_free()
385 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc, in stm32_mdma_desc_free()
386 desc->node[i].hwdesc_phys); in stm32_mdma_desc_free()
398 return ffs(width) - 1; in stm32_mdma_get_width()
402 return -EINVAL; in stm32_mdma_get_width()
406 static enum dma_slave_buswidth stm32_mdma_get_max_width(dma_addr_t addr, in stm32_mdma_get_max_width() argument
418 if ((((buf_len | addr) & (max_width - 1)) == 0) && in stm32_mdma_get_max_width()
443 id = chan->id; in stm32_mdma_disable_chan()
455 dmadev->base + STM32_MDMA_CISR(id), cisr, in stm32_mdma_disable_chan()
459 return -EBUSY; in stm32_mdma_disable_chan()
478 status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id)); in stm32_mdma_stop()
482 stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(chan->id), status); in stm32_mdma_stop()
485 chan->busy = false; in stm32_mdma_stop()
494 /* Check if memory device is on AHB or AXI */ in stm32_mdma_set_bus()
497 for (i = 0; i < dmadev->nr_ahb_addr_masks; i++) { in stm32_mdma_set_bus()
498 if (mask == dmadev->ahb_addr_masks[i]) { in stm32_mdma_set_bus()
508 u32 *mdma_ctbr, dma_addr_t addr, in stm32_mdma_set_xfer_param() argument
512 struct stm32_mdma_chan_config *chan_config = &chan->chan_config; in stm32_mdma_set_xfer_param()
519 src_addr_width = chan->dma_config.src_addr_width; in stm32_mdma_set_xfer_param()
520 dst_addr_width = chan->dma_config.dst_addr_width; in stm32_mdma_set_xfer_param()
521 src_maxburst = chan->dma_config.src_maxburst; in stm32_mdma_set_xfer_param()
522 dst_maxburst = chan->dma_config.dst_maxburst; in stm32_mdma_set_xfer_param()
524 ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); in stm32_mdma_set_xfer_param()
525 ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); in stm32_mdma_set_xfer_param()
526 ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); in stm32_mdma_set_xfer_param()
533 ctcr |= chan_config->transfer_config & STM32_MDMA_CTCR_CFG_MASK; in stm32_mdma_set_xfer_param()
537 * the number of bytes - 1 in CTCR register in stm32_mdma_set_xfer_param()
541 ctcr |= STM32_MDMA_CTCR_TLEN((tlen - 1)); in stm32_mdma_set_xfer_param()
552 return -EINVAL; in stm32_mdma_set_xfer_param()
558 return -EINVAL; in stm32_mdma_set_xfer_param()
563 * - Clear SW request as in this case this is a HW one in stm32_mdma_set_xfer_param()
564 * - Clear WEX, HEX and BEX bits in stm32_mdma_set_xfer_param()
565 * - Set priority level in stm32_mdma_set_xfer_param()
569 ccr |= STM32_MDMA_CCR_PL(chan_config->priority_level); in stm32_mdma_set_xfer_param()
573 ctbr |= STM32_MDMA_CTBR_TSEL(chan_config->request); in stm32_mdma_set_xfer_param()
577 dst_addr = chan->dma_config.dst_addr; in stm32_mdma_set_xfer_param()
590 chan->mem_burst = dst_best_burst; in stm32_mdma_set_xfer_param()
595 src_addr_width = stm32_mdma_get_max_width(addr, buf_len, tlen); in stm32_mdma_set_xfer_param()
596 chan->mem_width = src_addr_width; in stm32_mdma_set_xfer_param()
610 chan->mem_burst = src_best_burst; in stm32_mdma_set_xfer_param()
622 stm32_mdma_write(dmadev, STM32_MDMA_CDAR(chan->id), dst_addr); in stm32_mdma_set_xfer_param()
626 src_addr = chan->dma_config.src_addr; in stm32_mdma_set_xfer_param()
643 dst_addr_width = stm32_mdma_get_max_width(addr, buf_len, tlen); in stm32_mdma_set_xfer_param()
644 chan->mem_width = dst_addr_width; in stm32_mdma_set_xfer_param()
669 stm32_mdma_write(dmadev, STM32_MDMA_CSAR(chan->id), src_addr); in stm32_mdma_set_xfer_param()
674 return -EINVAL; in stm32_mdma_set_xfer_param()
687 dev_dbg(chan2dev(chan), "hwdesc: %pad\n", &node->hwdesc_phys); in stm32_mdma_dump_hwdesc()
688 dev_dbg(chan2dev(chan), "CTCR: 0x%08x\n", node->hwdesc->ctcr); in stm32_mdma_dump_hwdesc()
689 dev_dbg(chan2dev(chan), "CBNDTR: 0x%08x\n", node->hwdesc->cbndtr); in stm32_mdma_dump_hwdesc()
690 dev_dbg(chan2dev(chan), "CSAR: 0x%08x\n", node->hwdesc->csar); in stm32_mdma_dump_hwdesc()
691 dev_dbg(chan2dev(chan), "CDAR: 0x%08x\n", node->hwdesc->cdar); in stm32_mdma_dump_hwdesc()
692 dev_dbg(chan2dev(chan), "CBRUR: 0x%08x\n", node->hwdesc->cbrur); in stm32_mdma_dump_hwdesc()
693 dev_dbg(chan2dev(chan), "CLAR: 0x%08x\n", node->hwdesc->clar); in stm32_mdma_dump_hwdesc()
694 dev_dbg(chan2dev(chan), "CTBR: 0x%08x\n", node->hwdesc->ctbr); in stm32_mdma_dump_hwdesc()
695 dev_dbg(chan2dev(chan), "CMAR: 0x%08x\n", node->hwdesc->cmar); in stm32_mdma_dump_hwdesc()
696 dev_dbg(chan2dev(chan), "CMDR: 0x%08x\n\n", node->hwdesc->cmdr); in stm32_mdma_dump_hwdesc()
706 struct stm32_mdma_chan_config *config = &chan->chan_config; in stm32_mdma_setup_hwdesc()
710 hwdesc = desc->node[count].hwdesc; in stm32_mdma_setup_hwdesc()
711 hwdesc->ctcr = ctcr; in stm32_mdma_setup_hwdesc()
712 hwdesc->cbndtr &= ~(STM32_MDMA_CBNDTR_BRC_MK | in stm32_mdma_setup_hwdesc()
716 hwdesc->cbndtr |= STM32_MDMA_CBNDTR_BNDT(len); in stm32_mdma_setup_hwdesc()
717 hwdesc->csar = src_addr; in stm32_mdma_setup_hwdesc()
718 hwdesc->cdar = dst_addr; in stm32_mdma_setup_hwdesc()
719 hwdesc->cbrur = 0; in stm32_mdma_setup_hwdesc()
720 hwdesc->ctbr = ctbr; in stm32_mdma_setup_hwdesc()
721 hwdesc->cmar = config->mask_addr; in stm32_mdma_setup_hwdesc()
722 hwdesc->cmdr = config->mask_data; in stm32_mdma_setup_hwdesc()
726 hwdesc->clar = desc->node[0].hwdesc_phys; in stm32_mdma_setup_hwdesc()
728 hwdesc->clar = 0; in stm32_mdma_setup_hwdesc()
730 hwdesc->clar = desc->node[next].hwdesc_phys; in stm32_mdma_setup_hwdesc()
733 stm32_mdma_dump_hwdesc(chan, &desc->node[count]); in stm32_mdma_setup_hwdesc()
742 struct dma_slave_config *dma_config = &chan->dma_config; in stm32_mdma_setup_xfer()
751 return -EINVAL; in stm32_mdma_setup_xfer()
756 dst_addr = dma_config->dst_addr; in stm32_mdma_setup_xfer()
763 src_addr = dma_config->src_addr; in stm32_mdma_setup_xfer()
777 i == sg_len - 1, i == 0, false); in stm32_mdma_setup_xfer()
785 desc->ccr = ccr; in stm32_mdma_setup_xfer()
804 if (chan->desc && chan->desc->cyclic) { in stm32_mdma_prep_slave_sg()
818 desc->cyclic = false; in stm32_mdma_prep_slave_sg()
820 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_mdma_prep_slave_sg()
823 for (i = 0; i < desc->count; i++) in stm32_mdma_prep_slave_sg()
824 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc, in stm32_mdma_prep_slave_sg()
825 desc->node[i].hwdesc_phys); in stm32_mdma_prep_slave_sg()
838 struct dma_slave_config *dma_config = &chan->dma_config; in stm32_mdma_prep_dma_cyclic()
849 if (chan->desc && chan->desc->cyclic) { in stm32_mdma_prep_dma_cyclic()
892 desc->ccr = ccr; in stm32_mdma_prep_dma_cyclic()
898 dst_addr = dma_config->dst_addr; in stm32_mdma_prep_dma_cyclic()
900 src_addr = dma_config->src_addr; in stm32_mdma_prep_dma_cyclic()
906 i == count - 1, i == 0, true); in stm32_mdma_prep_dma_cyclic()
909 desc->cyclic = true; in stm32_mdma_prep_dma_cyclic()
911 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_mdma_prep_dma_cyclic()
914 for (i = 0; i < desc->count; i++) in stm32_mdma_prep_dma_cyclic()
915 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc, in stm32_mdma_prep_dma_cyclic()
916 desc->node[i].hwdesc_phys); in stm32_mdma_prep_dma_cyclic()
941 if (chan->desc && chan->desc->cyclic) { in stm32_mdma_prep_dma_memcpy()
952 ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); in stm32_mdma_prep_dma_memcpy()
953 ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); in stm32_mdma_prep_dma_memcpy()
954 ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); in stm32_mdma_prep_dma_memcpy()
955 cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id)); in stm32_mdma_prep_dma_memcpy()
998 ctcr |= STM32_MDMA_CTCR_TLEN((tlen - 1)); in stm32_mdma_prep_dma_memcpy()
1030 hwdesc = desc->node[0].hwdesc; in stm32_mdma_prep_dma_memcpy()
1031 hwdesc->ctcr = ctcr; in stm32_mdma_prep_dma_memcpy()
1032 hwdesc->cbndtr = cbndtr; in stm32_mdma_prep_dma_memcpy()
1033 hwdesc->csar = src; in stm32_mdma_prep_dma_memcpy()
1034 hwdesc->cdar = dest; in stm32_mdma_prep_dma_memcpy()
1035 hwdesc->cbrur = 0; in stm32_mdma_prep_dma_memcpy()
1036 hwdesc->clar = 0; in stm32_mdma_prep_dma_memcpy()
1037 hwdesc->ctbr = ctbr; in stm32_mdma_prep_dma_memcpy()
1038 hwdesc->cmar = 0; in stm32_mdma_prep_dma_memcpy()
1039 hwdesc->cmdr = 0; in stm32_mdma_prep_dma_memcpy()
1041 stm32_mdma_dump_hwdesc(chan, &desc->node[0]); in stm32_mdma_prep_dma_memcpy()
1045 STM32_MDMA_CTCR_TLEN((STM32_MDMA_MAX_BUF_LEN - 1)); in stm32_mdma_prep_dma_memcpy()
1051 xfer_count = min_t(size_t, len - offset, in stm32_mdma_prep_dma_memcpy()
1089 i == count - 1, i == 0, false); in stm32_mdma_prep_dma_memcpy()
1093 desc->ccr = ccr; in stm32_mdma_prep_dma_memcpy()
1095 desc->cyclic = false; in stm32_mdma_prep_dma_memcpy()
1097 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_mdma_prep_dma_memcpy()
1105 stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id))); in stm32_mdma_dump_reg()
1107 stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id))); in stm32_mdma_dump_reg()
1109 stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id))); in stm32_mdma_dump_reg()
1111 stm32_mdma_read(dmadev, STM32_MDMA_CSAR(chan->id))); in stm32_mdma_dump_reg()
1113 stm32_mdma_read(dmadev, STM32_MDMA_CDAR(chan->id))); in stm32_mdma_dump_reg()
1115 stm32_mdma_read(dmadev, STM32_MDMA_CBRUR(chan->id))); in stm32_mdma_dump_reg()
1117 stm32_mdma_read(dmadev, STM32_MDMA_CLAR(chan->id))); in stm32_mdma_dump_reg()
1119 stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id))); in stm32_mdma_dump_reg()
1121 stm32_mdma_read(dmadev, STM32_MDMA_CMAR(chan->id))); in stm32_mdma_dump_reg()
1123 stm32_mdma_read(dmadev, STM32_MDMA_CMDR(chan->id))); in stm32_mdma_dump_reg()
1131 u32 id = chan->id; in stm32_mdma_start_transfer()
1134 vdesc = vchan_next_desc(&chan->vchan); in stm32_mdma_start_transfer()
1136 chan->desc = NULL; in stm32_mdma_start_transfer()
1140 list_del(&vdesc->node); in stm32_mdma_start_transfer()
1142 chan->desc = to_stm32_mdma_desc(vdesc); in stm32_mdma_start_transfer()
1143 hwdesc = chan->desc->node[0].hwdesc; in stm32_mdma_start_transfer()
1144 chan->curr_hwdesc = 0; in stm32_mdma_start_transfer()
1146 stm32_mdma_write(dmadev, STM32_MDMA_CCR(id), chan->desc->ccr); in stm32_mdma_start_transfer()
1147 stm32_mdma_write(dmadev, STM32_MDMA_CTCR(id), hwdesc->ctcr); in stm32_mdma_start_transfer()
1148 stm32_mdma_write(dmadev, STM32_MDMA_CBNDTR(id), hwdesc->cbndtr); in stm32_mdma_start_transfer()
1149 stm32_mdma_write(dmadev, STM32_MDMA_CSAR(id), hwdesc->csar); in stm32_mdma_start_transfer()
1150 stm32_mdma_write(dmadev, STM32_MDMA_CDAR(id), hwdesc->cdar); in stm32_mdma_start_transfer()
1151 stm32_mdma_write(dmadev, STM32_MDMA_CBRUR(id), hwdesc->cbrur); in stm32_mdma_start_transfer()
1152 stm32_mdma_write(dmadev, STM32_MDMA_CLAR(id), hwdesc->clar); in stm32_mdma_start_transfer()
1153 stm32_mdma_write(dmadev, STM32_MDMA_CTBR(id), hwdesc->ctbr); in stm32_mdma_start_transfer()
1154 stm32_mdma_write(dmadev, STM32_MDMA_CMAR(id), hwdesc->cmar); in stm32_mdma_start_transfer()
1155 stm32_mdma_write(dmadev, STM32_MDMA_CMDR(id), hwdesc->cmdr); in stm32_mdma_start_transfer()
1168 if (hwdesc->ctcr & STM32_MDMA_CTCR_SWRM) { in stm32_mdma_start_transfer()
1173 chan->busy = true; in stm32_mdma_start_transfer()
1175 dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); in stm32_mdma_start_transfer()
1183 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_mdma_issue_pending()
1185 if (!vchan_issue_pending(&chan->vchan)) in stm32_mdma_issue_pending()
1188 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); in stm32_mdma_issue_pending()
1190 if (!chan->desc && !chan->busy) in stm32_mdma_issue_pending()
1194 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_mdma_issue_pending()
1203 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_mdma_pause()
1205 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_mdma_pause()
1208 dev_dbg(chan2dev(chan), "vchan %pK: pause\n", &chan->vchan); in stm32_mdma_pause()
1221 hwdesc = chan->desc->node[chan->curr_hwdesc].hwdesc; in stm32_mdma_resume()
1223 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_mdma_resume()
1225 /* Re-configure control register */ in stm32_mdma_resume()
1226 stm32_mdma_write(dmadev, STM32_MDMA_CCR(chan->id), chan->desc->ccr); in stm32_mdma_resume()
1229 status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id)); in stm32_mdma_resume()
1231 stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(chan->id), status); in stm32_mdma_resume()
1235 /* Re-start DMA */ in stm32_mdma_resume()
1236 reg = STM32_MDMA_CCR(chan->id); in stm32_mdma_resume()
1240 if (hwdesc->ctcr & STM32_MDMA_CTCR_SWRM) in stm32_mdma_resume()
1243 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_mdma_resume()
1245 dev_dbg(chan2dev(chan), "vchan %pK: resume\n", &chan->vchan); in stm32_mdma_resume()
1256 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_mdma_terminate_all()
1257 if (chan->desc) { in stm32_mdma_terminate_all()
1258 vchan_terminate_vdesc(&chan->desc->vdesc); in stm32_mdma_terminate_all()
1259 if (chan->busy) in stm32_mdma_terminate_all()
1261 chan->desc = NULL; in stm32_mdma_terminate_all()
1263 vchan_get_all_descriptors(&chan->vchan, &head); in stm32_mdma_terminate_all()
1264 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_mdma_terminate_all()
1266 vchan_dma_desc_free_list(&chan->vchan, &head); in stm32_mdma_terminate_all()
1275 vchan_synchronize(&chan->vchan); in stm32_mdma_synchronize()
1283 memcpy(&chan->dma_config, config, sizeof(*config)); in stm32_mdma_slave_config()
1293 struct stm32_mdma_hwdesc *hwdesc = desc->node[0].hwdesc; in stm32_mdma_desc_residue()
1298 for (i = curr_hwdesc + 1; i < desc->count; i++) { in stm32_mdma_desc_residue()
1299 hwdesc = desc->node[i].hwdesc; in stm32_mdma_desc_residue()
1300 residue += STM32_MDMA_CBNDTR_BNDT(hwdesc->cbndtr); in stm32_mdma_desc_residue()
1302 cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id)); in stm32_mdma_desc_residue()
1305 if (!chan->mem_burst) in stm32_mdma_desc_residue()
1308 burst_size = chan->mem_burst * chan->mem_width; in stm32_mdma_desc_residue()
1311 residue = residue - modulo + burst_size; in stm32_mdma_desc_residue()
1330 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_mdma_tx_status()
1332 vdesc = vchan_find_desc(&chan->vchan, cookie); in stm32_mdma_tx_status()
1333 if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) in stm32_mdma_tx_status()
1334 residue = stm32_mdma_desc_residue(chan, chan->desc, in stm32_mdma_tx_status()
1335 chan->curr_hwdesc); in stm32_mdma_tx_status()
1341 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_mdma_tx_status()
1348 vchan_cookie_complete(&chan->desc->vdesc); in stm32_mdma_xfer_end()
1349 chan->desc = NULL; in stm32_mdma_xfer_end()
1350 chan->busy = false; in stm32_mdma_xfer_end()
1363 status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0); in stm32_mdma_irq_handler()
1367 status = readl_relaxed(dmadev->base + STM32_MDMA_GISR1); in stm32_mdma_irq_handler()
1380 chan = &dmadev->chan[id]; in stm32_mdma_irq_handler()
1387 spin_lock(&chan->vchan.lock); in stm32_mdma_irq_handler()
1388 status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id)); in stm32_mdma_irq_handler()
1389 ien = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); in stm32_mdma_irq_handler()
1394 spin_unlock(&chan->vchan.lock); in stm32_mdma_irq_handler()
1402 reg = STM32_MDMA_CIFCR(chan->id); in stm32_mdma_irq_handler()
1406 id = chan->id; in stm32_mdma_irq_handler()
1407 status = readl_relaxed(dmadev->base + STM32_MDMA_CESR(id)); in stm32_mdma_irq_handler()
1423 chan->curr_hwdesc++; in stm32_mdma_irq_handler()
1424 if (chan->desc && chan->desc->cyclic) { in stm32_mdma_irq_handler()
1425 if (chan->curr_hwdesc == chan->desc->count) in stm32_mdma_irq_handler()
1426 chan->curr_hwdesc = 0; in stm32_mdma_irq_handler()
1427 vchan_cyclic_callback(&chan->desc->vdesc); in stm32_mdma_irq_handler()
1440 spin_unlock(&chan->vchan.lock); in stm32_mdma_irq_handler()
1452 chan->desc_pool = dmam_pool_create(dev_name(&c->dev->device), in stm32_mdma_alloc_chan_resources()
1453 c->device->dev, in stm32_mdma_alloc_chan_resources()
1457 if (!chan->desc_pool) { in stm32_mdma_alloc_chan_resources()
1459 return -ENOMEM; in stm32_mdma_alloc_chan_resources()
1462 ret = clk_prepare_enable(dmadev->clk); in stm32_mdma_alloc_chan_resources()
1470 clk_disable_unprepare(dmadev->clk); in stm32_mdma_alloc_chan_resources()
1481 dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); in stm32_mdma_free_chan_resources()
1483 if (chan->busy) { in stm32_mdma_free_chan_resources()
1484 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_mdma_free_chan_resources()
1486 chan->desc = NULL; in stm32_mdma_free_chan_resources()
1487 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_mdma_free_chan_resources()
1490 clk_disable_unprepare(dmadev->clk); in stm32_mdma_free_chan_resources()
1492 dmam_pool_destroy(chan->desc_pool); in stm32_mdma_free_chan_resources()
1493 chan->desc_pool = NULL; in stm32_mdma_free_chan_resources()
1499 struct stm32_mdma_device *dmadev = ofdma->of_dma_data; in stm32_mdma_of_xlate()
1504 if (dma_spec->args_count < 5) { in stm32_mdma_of_xlate()
1509 config.request = dma_spec->args[0]; in stm32_mdma_of_xlate()
1510 config.priority_level = dma_spec->args[1]; in stm32_mdma_of_xlate()
1511 config.transfer_config = dma_spec->args[2]; in stm32_mdma_of_xlate()
1512 config.mask_addr = dma_spec->args[3]; in stm32_mdma_of_xlate()
1513 config.mask_data = dma_spec->args[4]; in stm32_mdma_of_xlate()
1515 if (config.request >= dmadev->nr_requests) { in stm32_mdma_of_xlate()
1525 c = dma_get_any_slave_channel(&dmadev->ddev); in stm32_mdma_of_xlate()
1532 chan->chan_config = config; in stm32_mdma_of_xlate()
1538 { .compatible = "st,stm32h7-mdma", },
1553 of_node = pdev->dev.of_node; in stm32_mdma_probe()
1555 return -ENODEV; in stm32_mdma_probe()
1557 ret = device_property_read_u32(&pdev->dev, "dma-channels", in stm32_mdma_probe()
1561 dev_warn(&pdev->dev, "MDMA defaulting on %i channels\n", in stm32_mdma_probe()
1565 ret = device_property_read_u32(&pdev->dev, "dma-requests", in stm32_mdma_probe()
1569 dev_warn(&pdev->dev, "MDMA defaulting on %i request lines\n", in stm32_mdma_probe()
1573 count = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks", in stm32_mdma_probe()
1578 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev) + sizeof(u32) * count, in stm32_mdma_probe()
1581 return -ENOMEM; in stm32_mdma_probe()
1583 dmadev->nr_channels = nr_channels; in stm32_mdma_probe()
1584 dmadev->nr_requests = nr_requests; in stm32_mdma_probe()
1585 device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks", in stm32_mdma_probe()
1586 dmadev->ahb_addr_masks, in stm32_mdma_probe()
1588 dmadev->nr_ahb_addr_masks = count; in stm32_mdma_probe()
1591 dmadev->base = devm_ioremap_resource(&pdev->dev, res); in stm32_mdma_probe()
1592 if (IS_ERR(dmadev->base)) in stm32_mdma_probe()
1593 return PTR_ERR(dmadev->base); in stm32_mdma_probe()
1595 dmadev->clk = devm_clk_get(&pdev->dev, NULL); in stm32_mdma_probe()
1596 if (IS_ERR(dmadev->clk)) { in stm32_mdma_probe()
1597 ret = PTR_ERR(dmadev->clk); in stm32_mdma_probe()
1598 if (ret == -EPROBE_DEFER) in stm32_mdma_probe()
1599 dev_info(&pdev->dev, "Missing controller clock\n"); in stm32_mdma_probe()
1603 dmadev->rst = devm_reset_control_get(&pdev->dev, NULL); in stm32_mdma_probe()
1604 if (!IS_ERR(dmadev->rst)) { in stm32_mdma_probe()
1605 reset_control_assert(dmadev->rst); in stm32_mdma_probe()
1607 reset_control_deassert(dmadev->rst); in stm32_mdma_probe()
1610 dd = &dmadev->ddev; in stm32_mdma_probe()
1611 dma_cap_set(DMA_SLAVE, dd->cap_mask); in stm32_mdma_probe()
1612 dma_cap_set(DMA_PRIVATE, dd->cap_mask); in stm32_mdma_probe()
1613 dma_cap_set(DMA_CYCLIC, dd->cap_mask); in stm32_mdma_probe()
1614 dma_cap_set(DMA_MEMCPY, dd->cap_mask); in stm32_mdma_probe()
1615 dd->device_alloc_chan_resources = stm32_mdma_alloc_chan_resources; in stm32_mdma_probe()
1616 dd->device_free_chan_resources = stm32_mdma_free_chan_resources; in stm32_mdma_probe()
1617 dd->device_tx_status = stm32_mdma_tx_status; in stm32_mdma_probe()
1618 dd->device_issue_pending = stm32_mdma_issue_pending; in stm32_mdma_probe()
1619 dd->device_prep_slave_sg = stm32_mdma_prep_slave_sg; in stm32_mdma_probe()
1620 dd->device_prep_dma_cyclic = stm32_mdma_prep_dma_cyclic; in stm32_mdma_probe()
1621 dd->device_prep_dma_memcpy = stm32_mdma_prep_dma_memcpy; in stm32_mdma_probe()
1622 dd->device_config = stm32_mdma_slave_config; in stm32_mdma_probe()
1623 dd->device_pause = stm32_mdma_pause; in stm32_mdma_probe()
1624 dd->device_resume = stm32_mdma_resume; in stm32_mdma_probe()
1625 dd->device_terminate_all = stm32_mdma_terminate_all; in stm32_mdma_probe()
1626 dd->device_synchronize = stm32_mdma_synchronize; in stm32_mdma_probe()
1627 dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in stm32_mdma_probe()
1631 dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in stm32_mdma_probe()
1635 dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | in stm32_mdma_probe()
1637 dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in stm32_mdma_probe()
1638 dd->max_burst = STM32_MDMA_MAX_BURST; in stm32_mdma_probe()
1639 dd->dev = &pdev->dev; in stm32_mdma_probe()
1640 INIT_LIST_HEAD(&dd->channels); in stm32_mdma_probe()
1642 for (i = 0; i < dmadev->nr_channels; i++) { in stm32_mdma_probe()
1643 chan = &dmadev->chan[i]; in stm32_mdma_probe()
1644 chan->id = i; in stm32_mdma_probe()
1645 chan->vchan.desc_free = stm32_mdma_desc_free; in stm32_mdma_probe()
1646 vchan_init(&chan->vchan, dd); in stm32_mdma_probe()
1649 dmadev->irq = platform_get_irq(pdev, 0); in stm32_mdma_probe()
1650 if (dmadev->irq < 0) { in stm32_mdma_probe()
1651 dev_err(&pdev->dev, "failed to get IRQ\n"); in stm32_mdma_probe()
1652 return dmadev->irq; in stm32_mdma_probe()
1655 ret = devm_request_irq(&pdev->dev, dmadev->irq, stm32_mdma_irq_handler, in stm32_mdma_probe()
1656 0, dev_name(&pdev->dev), dmadev); in stm32_mdma_probe()
1658 dev_err(&pdev->dev, "failed to request IRQ\n"); in stm32_mdma_probe()
1668 dev_err(&pdev->dev, in stm32_mdma_probe()
1675 dev_info(&pdev->dev, "STM32 MDMA driver registered\n"); in stm32_mdma_probe()
1688 .name = "stm32-mdma",
1702 MODULE_AUTHOR("Pierre-Yves Mordret <pierre-yves.mordret@st.com>");