Lines Matching +full:tegra210 +full:- +full:ahub
2 * ADMA driver for Nvidia's Tegra210 ADMA controller.
28 #include "virt-dma.h"
85 * struct tegra_adma_chip_data - Tegra chip specific data
93 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
106 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
117 * struct tegra_adma_chan - Tegra ADMA channel information
139 * struct tegra_adma - Tegra ADMA controller information
159 writel(val, tdma->base_addr + reg); in tdma_write()
164 return readl(tdma->base_addr + reg); in tdma_read()
169 writel(val, tdc->chan_addr + reg); in tdma_ch_write()
174 return readl(tdc->chan_addr + reg); in tdma_ch_read()
190 return tdc->tdma->dev; in tdc2dev()
203 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig)); in tegra_adma_slave_config()
221 tdma->base_addr + ADMA_GLOBAL_SOFT_RESET, in tegra_adma_init()
235 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_alloc()
236 unsigned int sreq_index = tdc->sreq_index; in tegra_adma_request_alloc()
238 if (tdc->sreq_reserved) in tegra_adma_request_alloc()
239 return tdc->sreq_dir == direction ? 0 : -EINVAL; in tegra_adma_request_alloc()
244 dev_err(tdma->dev, "invalid DMA request\n"); in tegra_adma_request_alloc()
245 return -EINVAL; in tegra_adma_request_alloc()
248 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) { in tegra_adma_request_alloc()
249 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
250 return -EINVAL; in tegra_adma_request_alloc()
256 dev_err(tdma->dev, "invalid DMA request\n"); in tegra_adma_request_alloc()
257 return -EINVAL; in tegra_adma_request_alloc()
260 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) { in tegra_adma_request_alloc()
261 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
262 return -EINVAL; in tegra_adma_request_alloc()
267 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_alloc()
268 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_alloc()
269 return -EINVAL; in tegra_adma_request_alloc()
272 tdc->sreq_dir = direction; in tegra_adma_request_alloc()
273 tdc->sreq_reserved = true; in tegra_adma_request_alloc()
280 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_free()
282 if (!tdc->sreq_reserved) in tegra_adma_request_free()
285 switch (tdc->sreq_dir) { in tegra_adma_request_free()
287 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved); in tegra_adma_request_free()
291 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved); in tegra_adma_request_free()
295 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_free()
296 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_free()
300 tdc->sreq_reserved = false; in tegra_adma_request_free()
330 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS, in tegra_adma_stop()
337 kfree(tdc->desc); in tegra_adma_stop()
338 tdc->desc = NULL; in tegra_adma_stop()
343 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc); in tegra_adma_start()
350 list_del(&vd->node); in tegra_adma_start()
352 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_start()
359 ch_regs = &desc->ch_regs; in tegra_adma_start()
361 tdc->tx_buf_pos = 0; in tegra_adma_start()
362 tdc->tx_buf_count = 0; in tegra_adma_start()
363 tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc); in tegra_adma_start()
364 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_start()
365 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr); in tegra_adma_start()
366 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr); in tegra_adma_start()
367 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); in tegra_adma_start()
368 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); in tegra_adma_start()
373 tdc->desc = desc; in tegra_adma_start()
378 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_get_residue()
386 if (pos < tdc->tx_buf_pos) in tegra_adma_get_residue()
387 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos); in tegra_adma_get_residue()
389 tdc->tx_buf_count += pos - tdc->tx_buf_pos; in tegra_adma_get_residue()
391 periods_remaining = tdc->tx_buf_count % desc->num_periods; in tegra_adma_get_residue()
392 tdc->tx_buf_pos = pos; in tegra_adma_get_residue()
394 return desc->buf_len - (periods_remaining * desc->period_len); in tegra_adma_get_residue()
403 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_isr()
406 if (status == 0 || !tdc->desc) { in tegra_adma_isr()
407 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_isr()
411 vchan_cyclic_callback(&tdc->desc->vd); in tegra_adma_isr()
413 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_isr()
423 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
425 if (vchan_issue_pending(&tdc->vc)) { in tegra_adma_issue_pending()
426 if (!tdc->desc) in tegra_adma_issue_pending()
430 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
439 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
441 if (tdc->desc) in tegra_adma_terminate_all()
445 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_adma_terminate_all()
446 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
447 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_adma_terminate_all()
467 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_tx_status()
469 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_adma_tx_status()
471 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_tx_status()
472 residual = desc->ch_regs.tc; in tegra_adma_tx_status()
473 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) { in tegra_adma_tx_status()
479 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_tx_status()
491 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_set_xfer_params()
494 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS) in tegra_adma_set_xfer_params()
495 return -EINVAL; in tegra_adma_set_xfer_params()
500 burst_size = fls(tdc->sconfig.dst_maxburst); in tegra_adma_set_xfer_params()
501 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
502 ch_regs->ctrl = ADMA_CH_CTRL_TX_REQ(tdc->sreq_index); in tegra_adma_set_xfer_params()
503 ch_regs->src_addr = buf_addr; in tegra_adma_set_xfer_params()
508 burst_size = fls(tdc->sconfig.src_maxburst); in tegra_adma_set_xfer_params()
509 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
510 ch_regs->ctrl = ADMA_CH_CTRL_RX_REQ(tdc->sreq_index); in tegra_adma_set_xfer_params()
511 ch_regs->trg_addr = buf_addr; in tegra_adma_set_xfer_params()
516 return -EINVAL; in tegra_adma_set_xfer_params()
522 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) | in tegra_adma_set_xfer_params()
525 ch_regs->config |= ADMA_CH_CONFIG_BURST_SIZE(burst_size); in tegra_adma_set_xfer_params()
526 ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1); in tegra_adma_set_xfer_params()
527 ch_regs->fifo_ctrl = ADMA_CH_FIFO_CTRL_DEFAULT; in tegra_adma_set_xfer_params()
528 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK; in tegra_adma_set_xfer_params()
560 desc->buf_len = buf_len; in tegra_adma_prep_dma_cyclic()
561 desc->period_len = period_len; in tegra_adma_prep_dma_cyclic()
562 desc->num_periods = buf_len / period_len; in tegra_adma_prep_dma_cyclic()
569 return vchan_tx_prep(&tdc->vc, &desc->vd, flags); in tegra_adma_prep_dma_cyclic()
577 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc); in tegra_adma_alloc_chan_resources()
587 free_irq(tdc->irq, tdc); in tegra_adma_alloc_chan_resources()
591 dma_cookie_init(&tdc->vc.chan); in tegra_adma_alloc_chan_resources()
601 vchan_free_chan_resources(&tdc->vc); in tegra_adma_free_chan_resources()
602 tasklet_kill(&tdc->vc.task); in tegra_adma_free_chan_resources()
603 free_irq(tdc->irq, tdc); in tegra_adma_free_chan_resources()
606 tdc->sreq_index = 0; in tegra_adma_free_chan_resources()
607 tdc->sreq_dir = DMA_TRANS_NONE; in tegra_adma_free_chan_resources()
613 struct tegra_adma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
618 if (dma_spec->args_count != 1) in tegra_dma_of_xlate()
621 sreq_index = dma_spec->args[0]; in tegra_dma_of_xlate()
624 dev_err(tdma->dev, "DMA request must not be 0\n"); in tegra_dma_of_xlate()
628 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
633 tdc->sreq_index = sreq_index; in tegra_dma_of_xlate()
645 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); in tegra_adma_runtime_suspend()
646 if (!tdma->global_cmd) in tegra_adma_runtime_suspend()
649 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_suspend()
650 tdc = &tdma->channels[i]; in tegra_adma_runtime_suspend()
651 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_suspend()
652 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); in tegra_adma_runtime_suspend()
654 if (!ch_reg->cmd) in tegra_adma_runtime_suspend()
656 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC); in tegra_adma_runtime_suspend()
657 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR); in tegra_adma_runtime_suspend()
658 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR); in tegra_adma_runtime_suspend()
659 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_runtime_suspend()
660 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); in tegra_adma_runtime_suspend()
661 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG); in tegra_adma_runtime_suspend()
665 clk_disable_unprepare(tdma->ahub_clk); in tegra_adma_runtime_suspend()
677 ret = clk_prepare_enable(tdma->ahub_clk); in tegra_adma_runtime_resume()
679 dev_err(dev, "ahub clk_enable failed: %d\n", ret); in tegra_adma_runtime_resume()
682 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); in tegra_adma_runtime_resume()
684 if (!tdma->global_cmd) in tegra_adma_runtime_resume()
687 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_resume()
688 tdc = &tdma->channels[i]; in tegra_adma_runtime_resume()
689 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_resume()
691 if (!ch_reg->cmd) in tegra_adma_runtime_resume()
693 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc); in tegra_adma_runtime_resume()
694 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr); in tegra_adma_runtime_resume()
695 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr); in tegra_adma_runtime_resume()
696 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl); in tegra_adma_runtime_resume()
697 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); in tegra_adma_runtime_resume()
698 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config); in tegra_adma_runtime_resume()
699 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd); in tegra_adma_runtime_resume()
710 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
722 cdata = of_device_get_match_data(&pdev->dev); in tegra_adma_probe()
724 dev_err(&pdev->dev, "device match data not found\n"); in tegra_adma_probe()
725 return -ENODEV; in tegra_adma_probe()
728 tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels * in tegra_adma_probe()
731 return -ENOMEM; in tegra_adma_probe()
733 tdma->dev = &pdev->dev; in tegra_adma_probe()
734 tdma->nr_channels = cdata->nr_channels; in tegra_adma_probe()
738 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res); in tegra_adma_probe()
739 if (IS_ERR(tdma->base_addr)) in tegra_adma_probe()
740 return PTR_ERR(tdma->base_addr); in tegra_adma_probe()
742 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); in tegra_adma_probe()
743 if (IS_ERR(tdma->ahub_clk)) { in tegra_adma_probe()
744 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n"); in tegra_adma_probe()
745 return PTR_ERR(tdma->ahub_clk); in tegra_adma_probe()
748 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_adma_probe()
749 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_probe()
750 struct tegra_adma_chan *tdc = &tdma->channels[i]; in tegra_adma_probe()
752 tdc->chan_addr = tdma->base_addr + ADMA_CH_REG_OFFSET(i); in tegra_adma_probe()
754 tdc->irq = of_irq_get(pdev->dev.of_node, i); in tegra_adma_probe()
755 if (tdc->irq <= 0) { in tegra_adma_probe()
756 ret = tdc->irq ?: -ENXIO; in tegra_adma_probe()
760 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_adma_probe()
761 tdc->vc.desc_free = tegra_adma_desc_free; in tegra_adma_probe()
762 tdc->tdma = tdma; in tegra_adma_probe()
765 pm_runtime_enable(&pdev->dev); in tegra_adma_probe()
767 ret = pm_runtime_get_sync(&pdev->dev); in tegra_adma_probe()
769 pm_runtime_put_noidle(&pdev->dev); in tegra_adma_probe()
777 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
778 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
779 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_adma_probe()
781 tdma->dma_dev.dev = &pdev->dev; in tegra_adma_probe()
782 tdma->dma_dev.device_alloc_chan_resources = in tegra_adma_probe()
784 tdma->dma_dev.device_free_chan_resources = in tegra_adma_probe()
786 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending; in tegra_adma_probe()
787 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic; in tegra_adma_probe()
788 tdma->dma_dev.device_config = tegra_adma_slave_config; in tegra_adma_probe()
789 tdma->dma_dev.device_tx_status = tegra_adma_tx_status; in tegra_adma_probe()
790 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all; in tegra_adma_probe()
791 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
792 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
793 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in tegra_adma_probe()
794 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in tegra_adma_probe()
796 ret = dma_async_device_register(&tdma->dma_dev); in tegra_adma_probe()
798 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret); in tegra_adma_probe()
802 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_adma_probe()
805 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret); in tegra_adma_probe()
809 pm_runtime_put(&pdev->dev); in tegra_adma_probe()
811 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n", in tegra_adma_probe()
812 tdma->nr_channels); in tegra_adma_probe()
817 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_probe()
819 pm_runtime_put_sync(&pdev->dev); in tegra_adma_probe()
821 pm_runtime_disable(&pdev->dev); in tegra_adma_probe()
823 while (--i >= 0) in tegra_adma_probe()
824 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_probe()
834 of_dma_controller_free(pdev->dev.of_node); in tegra_adma_remove()
835 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_remove()
837 for (i = 0; i < tdma->nr_channels; ++i) in tegra_adma_remove()
838 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_remove()
840 pm_runtime_put_sync(&pdev->dev); in tegra_adma_remove()
841 pm_runtime_disable(&pdev->dev); in tegra_adma_remove()
861 .name = "tegra-adma",
871 MODULE_ALIAS("platform:tegra210-adma");