Lines Matching full:ecc
216 struct edma_cc *ecc; member
290 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
292 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
295 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
297 __raw_writel(val, ecc->base + offset); in edma_write()
300 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
303 unsigned val = edma_read(ecc, offset); in edma_modify()
307 edma_write(ecc, offset, val); in edma_modify()
310 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) in edma_and() argument
312 unsigned val = edma_read(ecc, offset); in edma_and()
315 edma_write(ecc, offset, val); in edma_and()
318 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) in edma_or() argument
320 unsigned val = edma_read(ecc, offset); in edma_or()
323 edma_write(ecc, offset, val); in edma_or()
326 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, in edma_read_array() argument
329 return edma_read(ecc, offset + (i << 2)); in edma_read_array()
332 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, in edma_write_array() argument
335 edma_write(ecc, offset + (i << 2), val); in edma_write_array()
338 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, in edma_modify_array() argument
341 edma_modify(ecc, offset + (i << 2), and, or); in edma_modify_array()
344 static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, in edma_or_array() argument
347 edma_or(ecc, offset + (i << 2), or); in edma_or_array()
350 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, in edma_or_array2() argument
353 edma_or(ecc, offset + ((i * 2 + j) << 2), or); in edma_or_array2()
356 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, in edma_write_array2() argument
359 edma_write(ecc, offset + ((i * 2 + j) << 2), val); in edma_write_array2()
362 static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset) in edma_shadow0_read() argument
364 return edma_read(ecc, EDMA_SHADOW0 + offset); in edma_shadow0_read()
367 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, in edma_shadow0_read_array() argument
370 return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2)); in edma_shadow0_read_array()
373 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, in edma_shadow0_write() argument
376 edma_write(ecc, EDMA_SHADOW0 + offset, val); in edma_shadow0_write()
379 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, in edma_shadow0_write_array() argument
382 edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); in edma_shadow0_write_array()
385 static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset, in edma_param_read() argument
388 return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); in edma_param_read()
391 static inline void edma_param_write(struct edma_cc *ecc, int offset, in edma_param_write() argument
394 edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); in edma_param_write()
397 static inline void edma_param_modify(struct edma_cc *ecc, int offset, in edma_param_modify() argument
400 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); in edma_param_modify()
403 static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no, in edma_param_and() argument
406 edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); in edma_param_and()
409 static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, in edma_param_or() argument
412 edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); in edma_param_or()
421 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, in edma_assign_priority_to_queue() argument
426 edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); in edma_assign_priority_to_queue()
431 struct edma_cc *ecc = echan->ecc; in edma_set_chmap() local
434 if (ecc->chmap_exist) { in edma_set_chmap()
436 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); in edma_set_chmap()
442 struct edma_cc *ecc = echan->ecc; in edma_setup_interrupt() local
446 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5, in edma_setup_interrupt()
448 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5, in edma_setup_interrupt()
451 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5, in edma_setup_interrupt()
459 static void edma_write_slot(struct edma_cc *ecc, unsigned slot, in edma_write_slot() argument
463 if (slot >= ecc->num_slots) in edma_write_slot()
465 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); in edma_write_slot()
468 static int edma_read_slot(struct edma_cc *ecc, unsigned slot, in edma_read_slot() argument
472 if (slot >= ecc->num_slots) in edma_read_slot()
474 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); in edma_read_slot()
481 * @ecc: pointer to edma_cc struct
494 static int edma_alloc_slot(struct edma_cc *ecc, int slot) in edma_alloc_slot() argument
499 if (ecc->chmap_exist && slot < ecc->num_channels) in edma_alloc_slot()
504 if (ecc->chmap_exist) in edma_alloc_slot()
507 slot = ecc->num_channels; in edma_alloc_slot()
509 slot = find_next_zero_bit(ecc->slot_inuse, in edma_alloc_slot()
510 ecc->num_slots, in edma_alloc_slot()
512 if (slot == ecc->num_slots) in edma_alloc_slot()
514 if (!test_and_set_bit(slot, ecc->slot_inuse)) in edma_alloc_slot()
517 } else if (slot >= ecc->num_slots) { in edma_alloc_slot()
519 } else if (test_and_set_bit(slot, ecc->slot_inuse)) { in edma_alloc_slot()
523 edma_write_slot(ecc, slot, &dummy_paramset); in edma_alloc_slot()
525 return EDMA_CTLR_CHAN(ecc->id, slot); in edma_alloc_slot()
528 static void edma_free_slot(struct edma_cc *ecc, unsigned slot) in edma_free_slot() argument
531 if (slot >= ecc->num_slots) in edma_free_slot()
534 edma_write_slot(ecc, slot, &dummy_paramset); in edma_free_slot()
535 clear_bit(slot, ecc->slot_inuse); in edma_free_slot()
540 * @ecc: pointer to edma_cc struct
546 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) in edma_link() argument
549 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); in edma_link()
553 if (from >= ecc->num_slots || to >= ecc->num_slots) in edma_link()
556 edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, in edma_link()
562 * @ecc: pointer to edma_cc struct
568 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, in edma_get_position() argument
577 return edma_read(ecc, offs); in edma_get_position()
588 struct edma_cc *ecc = echan->ecc; in edma_start() local
595 dev_dbg(ecc->dev, "ESR%d %08x\n", j, in edma_start()
596 edma_shadow0_read_array(ecc, SH_ESR, j)); in edma_start()
597 edma_shadow0_write_array(ecc, SH_ESR, j, mask); in edma_start()
600 dev_dbg(ecc->dev, "ER%d %08x\n", j, in edma_start()
601 edma_shadow0_read_array(ecc, SH_ER, j)); in edma_start()
603 edma_write_array(ecc, EDMA_ECR, j, mask); in edma_start()
604 edma_write_array(ecc, EDMA_EMCR, j, mask); in edma_start()
606 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_start()
607 edma_shadow0_write_array(ecc, SH_EESR, j, mask); in edma_start()
608 dev_dbg(ecc->dev, "EER%d %08x\n", j, in edma_start()
609 edma_shadow0_read_array(ecc, SH_EER, j)); in edma_start()
615 struct edma_cc *ecc = echan->ecc; in edma_stop() local
620 edma_shadow0_write_array(ecc, SH_EECR, j, mask); in edma_stop()
621 edma_shadow0_write_array(ecc, SH_ECR, j, mask); in edma_stop()
622 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_stop()
623 edma_write_array(ecc, EDMA_EMCR, j, mask); in edma_stop()
626 edma_shadow0_write_array(ecc, SH_ICR, j, mask); in edma_stop()
628 dev_dbg(ecc->dev, "EER%d %08x\n", j, in edma_stop()
629 edma_shadow0_read_array(ecc, SH_EER, j)); in edma_stop()
645 edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask); in edma_pause()
654 edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask); in edma_resume()
659 struct edma_cc *ecc = echan->ecc; in edma_trigger_channel() local
663 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); in edma_trigger_channel()
665 dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), in edma_trigger_channel()
666 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); in edma_trigger_channel()
671 struct edma_cc *ecc = echan->ecc; in edma_clean_channel() local
676 dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j)); in edma_clean_channel()
677 edma_shadow0_write_array(ecc, SH_ECR, j, mask); in edma_clean_channel()
679 edma_write_array(ecc, EDMA_EMCR, j, mask); in edma_clean_channel()
681 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_clean_channel()
682 edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); in edma_clean_channel()
689 struct edma_cc *ecc = echan->ecc; in edma_assign_channel_eventq() local
695 eventq_no = ecc->default_queue; in edma_assign_channel_eventq()
696 if (eventq_no >= ecc->num_tc) in edma_assign_channel_eventq()
700 edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), in edma_assign_channel_eventq()
707 struct edma_cc *ecc = echan->ecc; in edma_alloc_channel() local
711 edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); in edma_alloc_channel()
754 struct edma_cc *ecc = echan->ecc; in edma_execute() local
779 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); in edma_execute()
804 edma_link(ecc, echan->slot[i], echan->slot[i + 1]); in edma_execute()
816 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); in edma_execute()
818 edma_link(ecc, echan->slot[nslots - 1], in edma_execute()
819 echan->ecc->dummy_slot); in edma_execute()
1092 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_slave_sg()
1221 echan->slot[1] = edma_alloc_slot(echan->ecc, in edma_prep_dma_memcpy()
1333 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_dma_cyclic()
1445 struct edma_cc *ecc = data; in dma_irq_handler() local
1451 ctlr = ecc->id; in dma_irq_handler()
1455 dev_vdbg(ecc->dev, "dma_irq_handler\n"); in dma_irq_handler()
1457 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); in dma_irq_handler()
1459 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); in dma_irq_handler()
1462 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); in dma_irq_handler()
1465 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); in dma_irq_handler()
1479 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); in dma_irq_handler()
1480 edma_completion_handler(&ecc->slave_chans[channel]); in dma_irq_handler()
1484 edma_shadow0_write(ecc, SH_IEVAL, 1); in dma_irq_handler()
1490 struct edma_cc *ecc = echan->ecc; in edma_error_handler() local
1500 err = edma_read_slot(ecc, echan->slot[0], &p); in edma_error_handler()
1531 static inline bool edma_error_pending(struct edma_cc *ecc) in edma_error_pending() argument
1533 if (edma_read_array(ecc, EDMA_EMR, 0) || in edma_error_pending()
1534 edma_read_array(ecc, EDMA_EMR, 1) || in edma_error_pending()
1535 edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR)) in edma_error_pending()
1544 struct edma_cc *ecc = data; in dma_ccerr_handler() local
1550 ctlr = ecc->id; in dma_ccerr_handler()
1554 dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); in dma_ccerr_handler()
1556 if (!edma_error_pending(ecc)) { in dma_ccerr_handler()
1562 dev_err(ecc->dev, "%s: Error interrupt without error event!\n", in dma_ccerr_handler()
1564 edma_write(ecc, EDMA_EEVAL, 1); in dma_ccerr_handler()
1573 val = edma_read_array(ecc, EDMA_EMR, j); in dma_ccerr_handler()
1577 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); in dma_ccerr_handler()
1584 edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); in dma_ccerr_handler()
1586 edma_shadow0_write_array(ecc, SH_SECR, j, in dma_ccerr_handler()
1588 edma_error_handler(&ecc->slave_chans[k]); in dma_ccerr_handler()
1592 val = edma_read(ecc, EDMA_QEMR); in dma_ccerr_handler()
1594 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); in dma_ccerr_handler()
1596 edma_write(ecc, EDMA_QEMCR, val); in dma_ccerr_handler()
1597 edma_shadow0_write(ecc, SH_QSECR, val); in dma_ccerr_handler()
1600 val = edma_read(ecc, EDMA_CCERR); in dma_ccerr_handler()
1602 dev_warn(ecc->dev, "CCERR 0x%08x\n", val); in dma_ccerr_handler()
1604 edma_write(ecc, EDMA_CCERRCLR, val); in dma_ccerr_handler()
1607 if (!edma_error_pending(ecc)) in dma_ccerr_handler()
1613 edma_write(ecc, EDMA_EEVAL, 1); in dma_ccerr_handler()
1621 struct edma_cc *ecc = echan->ecc; in edma_alloc_chan_resources() local
1622 struct device *dev = ecc->dev; in edma_alloc_chan_resources()
1628 } else if (ecc->tc_list) { in edma_alloc_chan_resources()
1630 echan->tc = &ecc->tc_list[ecc->info->default_queue]; in edma_alloc_chan_resources()
1638 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); in edma_alloc_chan_resources()
1665 struct device *dev = echan->ecc->dev; in edma_free_chan_resources()
1676 edma_free_slot(echan->ecc, echan->slot[i]); in edma_free_chan_resources()
1682 edma_set_chmap(echan, echan->ecc->dummy_slot); in edma_free_chan_resources()
1731 pos = edma_get_position(echan->ecc, echan->slot[0], dst); in edma_residue()
1741 while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) { in edma_residue()
1743 if (edma_get_position(echan->ecc, in edma_residue()
1834 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) in edma_dma_init() argument
1836 struct dma_device *s_ddev = &ecc->dma_slave; in edma_dma_init()
1838 s32 *memcpy_channels = ecc->info->memcpy_channels; in edma_dma_init()
1844 if (ecc->legacy_mode && !memcpy_channels) { in edma_dma_init()
1845 dev_warn(ecc->dev, in edma_dma_init()
1871 s_ddev->dev = ecc->dev; in edma_dma_init()
1875 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); in edma_dma_init()
1877 dev_warn(ecc->dev, "memcpy is disabled due to OoM\n"); in edma_dma_init()
1881 ecc->dma_memcpy = m_ddev; in edma_dma_init()
1902 m_ddev->dev = ecc->dev; in edma_dma_init()
1904 } else if (!ecc->legacy_mode) { in edma_dma_init()
1905 dev_info(ecc->dev, "memcpy is disabled\n"); in edma_dma_init()
1909 for (i = 0; i < ecc->num_channels; i++) { in edma_dma_init()
1910 struct edma_chan *echan = &ecc->slave_chans[i]; in edma_dma_init()
1911 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); in edma_dma_init()
1912 echan->ecc = ecc; in edma_dma_init()
1927 struct edma_cc *ecc) in edma_setup_from_hw() argument
1934 cccfg = edma_read(ecc, EDMA_CCCFG); in edma_setup_from_hw()
1937 ecc->num_region = BIT(value); in edma_setup_from_hw()
1940 ecc->num_channels = BIT(value + 1); in edma_setup_from_hw()
1943 ecc->num_qchannels = value * 2; in edma_setup_from_hw()
1946 ecc->num_slots = BIT(value + 4); in edma_setup_from_hw()
1949 ecc->num_tc = value + 1; in edma_setup_from_hw()
1951 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; in edma_setup_from_hw()
1954 dev_dbg(dev, "num_region: %u\n", ecc->num_region); in edma_setup_from_hw()
1955 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); in edma_setup_from_hw()
1956 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); in edma_setup_from_hw()
1957 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); in edma_setup_from_hw()
1958 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); in edma_setup_from_hw()
1959 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); in edma_setup_from_hw()
1975 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), in edma_setup_from_hw()
1980 for (i = 0; i < ecc->num_tc; i++) { in edma_setup_from_hw()
2140 struct edma_cc *ecc = ofdma->of_dma_data; in of_edma_xlate() local
2145 if (!ecc || dma_spec->args_count < 1) in of_edma_xlate()
2148 for (i = 0; i < ecc->num_channels; i++) { in of_edma_xlate()
2149 echan = &ecc->slave_chans[i]; in of_edma_xlate()
2159 if (echan->ecc->legacy_mode && dma_spec->args_count == 1) in of_edma_xlate()
2162 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && in of_edma_xlate()
2163 dma_spec->args[1] < echan->ecc->num_tc) { in of_edma_xlate()
2164 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; in of_edma_xlate()
2200 struct edma_cc *ecc; in edma_probe() local
2232 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); in edma_probe()
2233 if (!ecc) in edma_probe()
2236 ecc->dev = dev; in edma_probe()
2237 ecc->id = pdev->id; in edma_probe()
2238 ecc->legacy_mode = legacy_mode; in edma_probe()
2240 if (ecc->id < 0) in edma_probe()
2241 ecc->id = 0; in edma_probe()
2252 ecc->base = devm_ioremap_resource(dev, mem); in edma_probe()
2253 if (IS_ERR(ecc->base)) in edma_probe()
2254 return PTR_ERR(ecc->base); in edma_probe()
2256 platform_set_drvdata(pdev, ecc); in edma_probe()
2259 ret = edma_setup_from_hw(dev, info, ecc); in edma_probe()
2264 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, in edma_probe()
2265 sizeof(*ecc->slave_chans), GFP_KERNEL); in edma_probe()
2266 if (!ecc->slave_chans) in edma_probe()
2269 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), in edma_probe()
2271 if (!ecc->slot_inuse) in edma_probe()
2274 ecc->default_queue = info->default_queue; in edma_probe()
2283 edma_set_bits(off, ln, ecc->slot_inuse); in edma_probe()
2288 for (i = 0; i < ecc->num_slots; i++) { in edma_probe()
2290 if (!test_bit(i, ecc->slot_inuse)) in edma_probe()
2291 edma_write_slot(ecc, i, &dummy_paramset); in edma_probe()
2310 ecc); in edma_probe()
2315 ecc->ccint = irq; in edma_probe()
2326 ecc); in edma_probe()
2331 ecc->ccerrint = irq; in edma_probe()
2334 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); in edma_probe()
2335 if (ecc->dummy_slot < 0) { in edma_probe()
2337 return ecc->dummy_slot; in edma_probe()
2342 if (!ecc->legacy_mode) { in edma_probe()
2346 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, in edma_probe()
2347 sizeof(*ecc->tc_list), GFP_KERNEL); in edma_probe()
2348 if (!ecc->tc_list) { in edma_probe()
2356 if (ret || i == ecc->num_tc) in edma_probe()
2359 ecc->tc_list[i].node = tc_args.np; in edma_probe()
2360 ecc->tc_list[i].id = i; in edma_probe()
2371 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], in edma_probe()
2374 for (i = 0; i < ecc->num_region; i++) { in edma_probe()
2375 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); in edma_probe()
2376 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); in edma_probe()
2377 edma_write_array(ecc, EDMA_QRAE, i, 0x0); in edma_probe()
2379 ecc->info = info; in edma_probe()
2382 edma_dma_init(ecc, legacy_mode); in edma_probe()
2384 for (i = 0; i < ecc->num_channels; i++) { in edma_probe()
2386 edma_assign_channel_eventq(&ecc->slave_chans[i], in edma_probe()
2389 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); in edma_probe()
2392 ecc->dma_slave.filter.map = info->slave_map; in edma_probe()
2393 ecc->dma_slave.filter.mapcnt = info->slavecnt; in edma_probe()
2394 ecc->dma_slave.filter.fn = edma_filter_fn; in edma_probe()
2396 ret = dma_async_device_register(&ecc->dma_slave); in edma_probe()
2402 if (ecc->dma_memcpy) { in edma_probe()
2403 ret = dma_async_device_register(ecc->dma_memcpy); in edma_probe()
2407 dma_async_device_unregister(&ecc->dma_slave); in edma_probe()
2413 of_dma_controller_register(node, of_edma_xlate, ecc); in edma_probe()
2420 edma_free_slot(ecc, ecc->dummy_slot); in edma_probe()
2438 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_remove() local
2440 devm_free_irq(dev, ecc->ccint, ecc); in edma_remove()
2441 devm_free_irq(dev, ecc->ccerrint, ecc); in edma_remove()
2443 edma_cleanupp_vchan(&ecc->dma_slave); in edma_remove()
2447 dma_async_device_unregister(&ecc->dma_slave); in edma_remove()
2448 if (ecc->dma_memcpy) in edma_remove()
2449 dma_async_device_unregister(ecc->dma_memcpy); in edma_remove()
2450 edma_free_slot(ecc, ecc->dummy_slot); in edma_remove()
2458 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_pm_suspend() local
2459 struct edma_chan *echan = ecc->slave_chans; in edma_pm_suspend()
2462 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_suspend()
2472 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_pm_resume() local
2473 struct edma_chan *echan = ecc->slave_chans; in edma_pm_resume()
2478 edma_write_slot(ecc, ecc->dummy_slot, &dummy_paramset); in edma_pm_resume()
2480 queue_priority_mapping = ecc->info->queue_priority_mapping; in edma_pm_resume()
2484 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], in edma_pm_resume()
2487 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_resume()
2490 edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, in edma_pm_resume()