Lines Matching +full:memory +full:- +full:controller

16 	  EDAC is a subsystem along with hardware-specific drivers designed to
17 	  report hardware errors. These are low-level errors that are reported
19 	  memory errors, cache errors, PCI errors, thermal throttling, etc..
22 	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 	  levels are 0-4 (from low to high) and by default it is set to 2.
44 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
47 	---help---
49 	  occurring on your machine in human-readable form.
59 	  Not all machines support hardware-driven error report. Some of those
60 	  provide a BIOS-driven error report mechanism via ACPI, using the
64 	  When this option is enabled, it will disable the hardware-driven
68 	  It should be noticed that keeping both GHES and a hardware-driven
82 	  the AMD64 families (>= K8) of memory controllers.
88 	  Recent Opterons (Family 10h and later) provide for Memory Error
93 	  When enabled, in each of the respective memory controller directories
96 	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 	  - inject_word (0..8, 16-bit word of 16-byte section),
98 	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
130 	  82443BX/GX memory controllers (440BX/GX chipsets).
165 	  E3-1200 based DRAM controllers.
186 	  i7 Core (Nehalem) Integrated Memory Controller that exists on
226 	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
230 	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
239 	  Skylake server Integrated Memory Controllers. If your
240 	  system has non-volatile DIMMs you should also manually
248 	  Pondicherry2 Integrated Memory Controller. This SoC IP is
250 	  micro-server but may appear on others in the future.
263 	  Support for error detection and correction on Freescale memory
281 	tristate "Cell Broadband Engine memory controller"
285 	  Cell Broadband Engine internal memory controller
289 	tristate "PPC4xx IBM DDR2 Memory Controller"
292 	  This enables support for EDAC on the ECC memory used
293 	  with the IBM DDR2 memory controller found in various
298 	tristate "AMD8131 HyperTransport PCI-X Tunnel"
302 	  AMD8131 HyperTransport PCI-X Tunnel chip.
316 	tristate "IBM CPC925 Memory Controller (PPC970FX)"
320 	  IBM CPC925 Bridge and Memory Controller, which is
325 	tristate "Highbank Memory Controller"
329 	  Calxeda Highbank memory controller.
336 	  Calxeda Highbank memory controller.
353 	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
360 	tristate "Cavium Octeon PCI Controller"
372 	  Cavium ThunderX memory controllers (LMC), Cache
390 	  Altera L2 cache Memory for Altera SoCs. This option
394 	bool "Altera On-Chip RAM ECC"
398 	  Altera On-Chip RAM Memory for Altera SoCs.
405 	  Altera Ethernet FIFO Memory for Altera SoCs.
412 	  Altera NAND FIFO Memory for Altera SoCs.
419 	  Altera DMA FIFO Memory for Altera SoCs.
426 	  Altera USB FIFO Memory for Altera SoCs.
433 	  Altera QSPI FIFO Memory for Altera SoCs.
440 	  Altera SDMMC FIFO Memory for Altera SoCs.
443 	tristate "Synopsys DDR Memory Controller"
447 	  memory controller.
450 	tristate "APM X-Gene SoC"
454 	  APM X-Gene family of SOCs.
457 	tristate "Texas Instruments DDR3 ECC Controller"