5  * Copyright (C) 2012 - 2014 Xilinx, Inc.
28 /* Number of cs_rows needed per memory controller */
31 /* Number of channels per memory controller */
42 /* Synopsys DDR memory controller registers that are relevant to ECC */
52 /* ECC data[31:0] register */
99  * struct ecc_error_info - ECC error log information
104  * @data:	Data causing the error
111 	u32 data;  member
115  * struct synps_ecc_status - ECC status information to report
129  * struct synps_edac_priv - DDR memory controller private instance data
130  * @baseaddr:	Base address of the DDR controller
145  * synps_edac_geterror_info - Get the current ecc error info
146  * @base:	Pointer to the base address of the ddr memory controller
162 	p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT;  in synps_edac_geterror_info()
163 	p->ue_cnt = regval & STAT_UECNT_MASK;  in synps_edac_geterror_info()
166 	if (!(p->ce_cnt && (regval & LOG_VALID)))  in synps_edac_geterror_info()
169 	p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT;  in synps_edac_geterror_info()
171 	p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;  in synps_edac_geterror_info()
172 	p->ceinfo.col = regval & ADDR_COL_MASK;  in synps_edac_geterror_info()
173 	p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;  in synps_edac_geterror_info()
174 	p->ceinfo.data = readl(base + CE_DATA_31_0_OFST);  in synps_edac_geterror_info()
175 	edac_dbg(3, "ce bit position: %d data: %d\n", p->ceinfo.bitpos,  in synps_edac_geterror_info()
176 		 p->ceinfo.data);  in synps_edac_geterror_info()
181 	if (!(p->ue_cnt && (regval & LOG_VALID)))  in synps_edac_geterror_info()
185 	p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;  in synps_edac_geterror_info()
186 	p->ueinfo.col = regval & ADDR_COL_MASK;  in synps_edac_geterror_info()
187 	p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;  in synps_edac_geterror_info()
188 	p->ueinfo.data = readl(base + UE_DATA_31_0_OFST);  in synps_edac_geterror_info()
199  * synps_edac_handle_error - Handle controller error types CE and UE
200  * @mci:	Pointer to the edac memory controller instance
203  * Handles the controller ECC correctable and un correctable error.
208 	struct synps_edac_priv *priv = mci->pvt_info;  in synps_edac_handle_error()
211 	if (p->ce_cnt) {  in synps_edac_handle_error()
212 		pinf = &p->ceinfo;  in synps_edac_handle_error()
213 		snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,  in synps_edac_handle_error()
215 			 "CE", pinf->row, pinf->bank, pinf->col);  in synps_edac_handle_error()
217 				     p->ce_cnt, 0, 0, 0, 0, 0, -1,  in synps_edac_handle_error()
218 				     priv->message, "");  in synps_edac_handle_error()
221 	if (p->ue_cnt) {  in synps_edac_handle_error()
222 		pinf = &p->ueinfo;  in synps_edac_handle_error()
223 		snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,  in synps_edac_handle_error()
225 			 "UE", pinf->row, pinf->bank, pinf->col);  in synps_edac_handle_error()
227 				     p->ue_cnt, 0, 0, 0, 0, 0, -1,  in synps_edac_handle_error()
228 				     priv->message, "");  in synps_edac_handle_error()
235  * synps_edac_check - Check controller for ECC errors
236  * @mci:	Pointer to the edac memory controller instance
242 	struct synps_edac_priv *priv = mci->pvt_info;  in synps_edac_check()
245 	status = synps_edac_geterror_info(priv->baseaddr, &priv->stat);  in synps_edac_check()
249 	priv->ce_cnt += priv->stat.ce_cnt;  in synps_edac_check()
250 	priv->ue_cnt += priv->stat.ue_cnt;  in synps_edac_check()
251 	synps_edac_handle_error(mci, &priv->stat);  in synps_edac_check()
254 		 priv->ce_cnt, priv->ue_cnt);  in synps_edac_check()
258  * synps_edac_get_dtype - Return the controller memory width
259  * @base:	Pointer to the ddr memory controller base address
261  * Get the EDAC device type width appropriate for the current controller
289  * synps_edac_get_eccstate - Return the controller ecc enable/disable status
290  * @base:	Pointer to the ddr memory controller base address
292  * Get the ECC enable/disable status for the controller
294  * Return: a ecc status boolean i.e true/false - enabled/disabled.
314  * synps_edac_get_memsize - reads the size of the attached memory device
328  * synps_edac_get_mtype - Returns controller memory type
331  * Get the EDAC memory type appropriate for the current controller
352  * synps_edac_init_csrows - Initialize the cs row data
353  * @mci:	Pointer to the edac memory controller instance
356  * controller instance
364 	struct synps_edac_priv *priv = mci->pvt_info;  in synps_edac_init_csrows()
368 	for (row = 0; row < mci->nr_csrows; row++) {  in synps_edac_init_csrows()
369 		csi = mci->csrows[row];  in synps_edac_init_csrows()
372 		for (j = 0; j < csi->nr_channels; j++) {  in synps_edac_init_csrows()
373 			dimm            = csi->channels[j]->dimm;  in synps_edac_init_csrows()
374 			dimm->edac_mode = EDAC_FLAG_SECDED;  in synps_edac_init_csrows()
375 			dimm->mtype     = synps_edac_get_mtype(priv->baseaddr);  in synps_edac_init_csrows()
376 			dimm->nr_pages  = (size >> PAGE_SHIFT) / csi->nr_channels;  in synps_edac_init_csrows()
377 			dimm->grain     = SYNPS_EDAC_ERR_GRAIN;  in synps_edac_init_csrows()
378 			dimm->dtype     = synps_edac_get_dtype(priv->baseaddr);  in synps_edac_init_csrows()
386  * synps_edac_mc_init - Initialize driver instance
387  * @mci:	Pointer to the edac memory controller instance
390  * Performs initialization of the EDAC memory controller instance and
391  * related driver-private data associated with the memory controller the
402 	mci->pdev = &pdev->dev;  in synps_edac_mc_init()
403 	priv = mci->pvt_info;  in synps_edac_mc_init()
406 	/* Initialize controller capabilities and configuration */  in synps_edac_mc_init()
407 	mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;  in synps_edac_mc_init()
408 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;  in synps_edac_mc_init()
409 	mci->scrub_cap = SCRUB_HW_SRC;  in synps_edac_mc_init()
410 	mci->scrub_mode = SCRUB_NONE;  in synps_edac_mc_init()
412 	mci->edac_cap = EDAC_FLAG_SECDED;  in synps_edac_mc_init()
413 	mci->ctl_name = "synps_ddr_controller";  in synps_edac_mc_init()
414 	mci->dev_name = SYNPS_EDAC_MOD_STRING;  in synps_edac_mc_init()
415 	mci->mod_name = SYNPS_EDAC_MOD_VER;  in synps_edac_mc_init()
418 	mci->edac_check = synps_edac_check;  in synps_edac_mc_init()
419 	mci->ctl_page_to_phys = NULL;  in synps_edac_mc_init()
427  * synps_edac_mc_probe - Check controller and bind driver
430  * Probes a specific controller instance for binding with the driver.
432  * Return: 0 if the controller instance was successfully bound to the
445 	baseaddr = devm_ioremap_resource(&pdev->dev, res);  in synps_edac_mc_probe()
451 		return -ENXIO;  in synps_edac_mc_probe()
466 		return -ENOMEM;  in synps_edac_mc_probe()
469 	priv = mci->pvt_info;  in synps_edac_mc_probe()
470 	priv->baseaddr = baseaddr;  in synps_edac_mc_probe()
499  * synps_edac_mc_remove - Unbind driver from controller
508 	edac_mc_del_mc(&pdev->dev);  in synps_edac_mc_remove()
515 	{ .compatible = "xlnx,zynq-ddrc-a05", },
523 		   .name = "synopsys-edac",