2  * Qualcomm SCM driver
117  * Set the Linux entry point for the SCM to transfer control to when coming
165  * @resp: response buffer passed to SCM
167  * Write HDCP register(s) through SCM.
221 	 * During the scm call memory protection will be enabled for the meta  in qcom_scm_pas_init_image()
417  * qcom_scm_is_available() - Checks if SCM is available
515 	struct qcom_scm *scm;  in qcom_scm_probe()  local
519 	scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);  in qcom_scm_probe()
520 	if (!scm)  in qcom_scm_probe()
523 	ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);  in qcom_scm_probe()
529 		scm->core_clk = devm_clk_get(&pdev->dev, "core");  in qcom_scm_probe()
530 		if (IS_ERR(scm->core_clk)) {  in qcom_scm_probe()
531 			if (PTR_ERR(scm->core_clk) != -EPROBE_DEFER)  in qcom_scm_probe()
534 			return PTR_ERR(scm->core_clk);  in qcom_scm_probe()
539 		scm->iface_clk = devm_clk_get(&pdev->dev, "iface");  in qcom_scm_probe()
540 		if (IS_ERR(scm->iface_clk)) {  in qcom_scm_probe()
541 			if (PTR_ERR(scm->iface_clk) != -EPROBE_DEFER)  in qcom_scm_probe()
544 			return PTR_ERR(scm->iface_clk);  in qcom_scm_probe()
549 		scm->bus_clk = devm_clk_get(&pdev->dev, "bus");  in qcom_scm_probe()
550 		if (IS_ERR(scm->bus_clk)) {  in qcom_scm_probe()
551 			if (PTR_ERR(scm->bus_clk) != -EPROBE_DEFER)  in qcom_scm_probe()
554 			return PTR_ERR(scm->bus_clk);  in qcom_scm_probe()
558 	scm->reset.ops = &qcom_scm_pas_reset_ops;  in qcom_scm_probe()
559 	scm->reset.nr_resets = 1;  in qcom_scm_probe()
560 	scm->reset.of_node = pdev->dev.of_node;  in qcom_scm_probe()
561 	ret = devm_reset_controller_register(&pdev->dev, &scm->reset);  in qcom_scm_probe()
566 	ret = clk_set_rate(scm->core_clk, INT_MAX);  in qcom_scm_probe()
570 	__scm = scm;  in qcom_scm_probe()
594 	{ .compatible = "qcom,scm-apq8064",
597 	{ .compatible = "qcom,scm-msm8660",
600 	{ .compatible = "qcom,scm-msm8960",
603 	{ .compatible = "qcom,scm-msm8996",
606 	{ .compatible = "qcom,scm-ipq4019",
609 	{ .compatible = "qcom,scm",