Lines Matching full:tx
56 * written through the tx.channel pointer, while the second is only written
70 } tx; member
105 u32 tx = READ_ONCE(header->tx.count); in tegra_ivc_empty() local
118 if (tx - rx > ivc->num_frames) in tegra_ivc_empty()
121 return tx == rx; in tegra_ivc_empty()
127 u32 tx = READ_ONCE(header->tx.count); in tegra_ivc_full() local
134 return tx - rx >= ivc->num_frames; in tegra_ivc_full()
140 u32 tx = READ_ONCE(header->tx.count); in tegra_ivc_available() local
149 return tx - rx; in tegra_ivc_available()
154 WRITE_ONCE(ivc->tx.channel->tx.count, in tegra_ivc_advance_tx()
155 READ_ONCE(ivc->tx.channel->tx.count) + 1); in tegra_ivc_advance_tx()
157 if (ivc->tx.position == ivc->num_frames - 1) in tegra_ivc_advance_tx()
158 ivc->tx.position = 0; in tegra_ivc_advance_tx()
160 ivc->tx.position++; in tegra_ivc_advance_tx()
176 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_check_read()
179 * tx.channel->state is set locally, so it is not synchronized with in tegra_ivc_check_read()
186 if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) in tegra_ivc_check_read()
211 if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) in tegra_ivc_check_write()
214 if (!tegra_ivc_full(ivc, ivc->tx.channel)) in tegra_ivc_check_write()
217 tegra_ivc_invalidate(ivc, ivc->tx.phys + offset); in tegra_ivc_check_write()
219 if (tegra_ivc_full(ivc, ivc->tx.channel)) in tegra_ivc_check_write()
302 unsigned int tx = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_read_advance() local
320 * ivc->tx.position. in tegra_ivc_read_advance()
329 tegra_ivc_invalidate(ivc, ivc->rx.phys + tx); in tegra_ivc_read_advance()
338 /* directly poke at the next frame to be tx'ed */
347 return tegra_ivc_frame_virt(ivc, ivc->tx.channel, ivc->tx.position); in tegra_ivc_write_get_next_frame()
351 /* advance the tx buffer */
354 unsigned int tx = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_write_advance() local
362 tegra_ivc_flush_frame(ivc, ivc->tx.phys, ivc->tx.position, 0, in tegra_ivc_write_advance()
367 * ivc->tx.position. in tegra_ivc_write_advance()
372 tegra_ivc_flush(ivc, ivc->tx.phys + tx); in tegra_ivc_write_advance()
375 * Ensure our write to ivc->tx.position occurs before our read from in tegra_ivc_write_advance()
385 tegra_ivc_invalidate(ivc, ivc->tx.phys + rx); in tegra_ivc_write_advance()
387 if (tegra_ivc_available(ivc, ivc->tx.channel) == 1) in tegra_ivc_write_advance()
396 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_reset()
398 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_SYNC; in tegra_ivc_reset()
399 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_reset()
426 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_notified()
431 state = READ_ONCE(ivc->rx.channel->tx.state); in tegra_ivc_notified()
434 offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_notified()
438 * clearing tx.channel. in tegra_ivc_notified()
443 * Reset tx.channel counters. The remote end is in the SYNC in tegra_ivc_notified()
447 ivc->tx.channel->tx.count = 0; in tegra_ivc_notified()
450 ivc->tx.position = 0; in tegra_ivc_notified()
463 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ACK; in tegra_ivc_notified()
464 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_notified()
471 } else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_SYNC && in tegra_ivc_notified()
473 offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_notified()
482 * Reset tx.channel counters. The remote end is in the ACK in tegra_ivc_notified()
486 ivc->tx.channel->tx.count = 0; in tegra_ivc_notified()
489 ivc->tx.position = 0; in tegra_ivc_notified()
503 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED; in tegra_ivc_notified()
504 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_notified()
511 } else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_ACK) { in tegra_ivc_notified()
512 offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_notified()
517 * peer state before storing to tx.channel. in tegra_ivc_notified()
527 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED; in tegra_ivc_notified()
528 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_notified()
544 if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) in tegra_ivc_notified()
569 static int tegra_ivc_check_params(unsigned long rx, unsigned long tx, in tegra_ivc_check_params() argument
572 BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, tx.count), in tegra_ivc_check_params()
598 if (!IS_ALIGNED(tx, TEGRA_IVC_ALIGN)) { in tegra_ivc_check_params()
599 pr_err("IVC channel start not aligned: %#lx\n", tx); in tegra_ivc_check_params()
603 if (rx < tx) { in tegra_ivc_check_params()
604 if (rx + frame_size * num_frames > tx) { in tegra_ivc_check_params()
606 rx, frame_size * num_frames, tx); in tegra_ivc_check_params()
610 if (tx + frame_size * num_frames > rx) { in tegra_ivc_check_params()
612 tx, frame_size * num_frames, rx); in tegra_ivc_check_params()
621 dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys, in tegra_ivc_init() argument
639 err = tegra_ivc_check_params((unsigned long)rx, (unsigned long)tx, in tegra_ivc_init()
652 ivc->tx.phys = dma_map_single(peer, tx, queue_size, in tegra_ivc_init()
654 if (dma_mapping_error(peer, ivc->tx.phys)) { in tegra_ivc_init()
661 ivc->tx.phys = tx_phys; in tegra_ivc_init()
665 ivc->tx.channel = tx; in tegra_ivc_init()
676 ivc->tx.position = 0; in tegra_ivc_init()
691 dma_unmap_single(ivc->peer, ivc->tx.phys, size, in tegra_ivc_cleanup()