Lines Matching full:fpga

2 # FPGA framework configuration
5 menuconfig FPGA  config
6 	tristate "FPGA Configuration Framework"
9 	  kernel.  The FPGA framework adds a FPGA manager class and FPGA
12 if FPGA
15 	tristate "Altera SOCFPGA FPGA Manager"
18 	  FPGA manager driver support for Altera SOCFPGA.
25 	  FPGA manager driver support for Altera Arria10 SoCFPGA.
40 	tristate "Altera FPGA Passive Serial over SPI"
44 	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
48 	tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager"
51 	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V
55 	tristate "Xilinx Zynq FPGA"
58 	  FPGA manager driver support for Xilinx Zynq FPGAs.
64 	  FPGA manager driver support for Xilinx FPGA configuration
71 	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
77 	  FPGA manager driver support for Lattice MachXO2 configuration
81 	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
84 	  FPGA manager driver support for the Altera Cyclone II FPGA
88 	tristate "FPGA Bridge Framework"
94 	tristate "Altera SoCFPGA FPGA Bridges"
97 	  Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
101 	tristate "Altera FPGA Freeze Bridge"
104 	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
105 	  freeze bridge is a bridge that exists in the FPGA fabric to
106 	  isolate one region of the FPGA from the busses while that
115 	  The PR Decoupler exists in the FPGA fabric to isolate one
116 	  region of the FPGA from the busses while that region is
120 	tristate "FPGA Region"
123 	  FPGA Region common code.  A FPGA Region controls a FPGA Manager
124 	  and the FPGA Bridges associated with either a reconfigurable
125 	  region of an FPGA or a whole FPGA.
128 	tristate "FPGA Region Device Tree Overlay Support"
131 	  Support for loading FPGA images by applying a Device Tree
135 	tristate "FPGA Device Feature List (DFL) support"
141 	  to provide an extensible way of adding features for FPGA.
143 	  devices (e.g. FPGA Management Engine, Port and Accelerator
144 	  Function Unit) and their private features for target FPGA devices.
147 	  Gate Array (FPGA) solutions which implement Device Feature List.
151 	tristate "FPGA DFL FME Driver"
154 	  The FPGA Management Engine (FME) is a feature device implemented
157 	  FPGA platform level management features. There shall be one FME
158 	  per DFL based FPGA device.
161 	tristate "FPGA DFL FME Manager Driver"
164 	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
167 	tristate "FPGA DFL FME Bridge Driver"
170 	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
173 	tristate "FPGA DFL FME Region Driver"
176 	  Say Y to enable FPGA Region driver for FPGA Management Engine.
179 	tristate "FPGA DFL AFU Driver"
182 	  This is the driver for FPGA Accelerated Function Unit (AFU) which
184 	  to the FPGA infrastructure via a Port. There may be more than one
185 	  Port/AFU per DFL based FPGA device.
188 	tristate "FPGA DFL PCIe Device Driver"
192 	  Field-Programmable Gate Array (FPGA) solutions which implement
195 	  FPGA accelerators on the FPGA DFL devices, enables system level
196 	  management functions such as FPGA partial reconfiguration, power
202 endif # FPGA