14 #include <linux/fpga/fpga-mgr.h>
37 	struct ice40_fpga_priv *priv = mgr->priv;  in ice40_fpga_ops_state()
39 	return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING :  in ice40_fpga_ops_state()
47 	struct ice40_fpga_priv *priv = mgr->priv;  in ice40_fpga_ops_write_init()
48 	struct spi_device *dev = priv->dev;  in ice40_fpga_ops_write_init()
59 	if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {  in ice40_fpga_ops_write_init()
60 		dev_err(&dev->dev,  in ice40_fpga_ops_write_init()
62 		return -ENOTSUPP;  in ice40_fpga_ops_write_init()
66 	spi_bus_lock(dev->master);  in ice40_fpga_ops_write_init()
68 	gpiod_set_value(priv->reset, 1);  in ice40_fpga_ops_write_init()
75 	gpiod_set_value(priv->reset, 0);  in ice40_fpga_ops_write_init()
77 	/* Abort if the chip-select failed */  in ice40_fpga_ops_write_init()
81 	/* Check CDONE is de-asserted i.e. the FPGA is reset */  in ice40_fpga_ops_write_init()
82 	if (gpiod_get_value(priv->cdone)) {  in ice40_fpga_ops_write_init()
83 		dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");  in ice40_fpga_ops_write_init()
84 		ret = -EIO;  in ice40_fpga_ops_write_init()
94 	spi_bus_unlock(dev->master);  in ice40_fpga_ops_write_init()
102 	struct ice40_fpga_priv *priv = mgr->priv;  in ice40_fpga_ops_write()
104 	return spi_write(priv->dev, buf, count);  in ice40_fpga_ops_write()
110 	struct ice40_fpga_priv *priv = mgr->priv;  in ice40_fpga_ops_write_complete()
111 	struct spi_device *dev = priv->dev;  in ice40_fpga_ops_write_complete()
114 	/* Check CDONE is asserted */  in ice40_fpga_ops_write_complete()
115 	if (!gpiod_get_value(priv->cdone)) {  in ice40_fpga_ops_write_complete()
116 		dev_err(&dev->dev,  in ice40_fpga_ops_write_complete()
117 			"CDONE was not asserted after firmware transfer\n");  in ice40_fpga_ops_write_complete()
118 		return -EIO;  in ice40_fpga_ops_write_complete()
121 	/* Send of zero-padding to activate the firmware */  in ice40_fpga_ops_write_complete()
134 	struct device *dev = &spi->dev;  in ice40_fpga_probe()
139 	priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);  in ice40_fpga_probe()
141 		return -ENOMEM;  in ice40_fpga_probe()
143 	priv->dev = spi;  in ice40_fpga_probe()
146 	if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) {  in ice40_fpga_probe()
149 		return -EINVAL;  in ice40_fpga_probe()
152 	if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) {  in ice40_fpga_probe()
155 		return -EINVAL;  in ice40_fpga_probe()
158 	if (spi->mode & SPI_CPHA) {  in ice40_fpga_probe()
160 		return -EINVAL;  in ice40_fpga_probe()
164 	priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);  in ice40_fpga_probe()
165 	if (IS_ERR(priv->cdone)) {  in ice40_fpga_probe()
166 		ret = PTR_ERR(priv->cdone);  in ice40_fpga_probe()
171 	priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);  in ice40_fpga_probe()
172 	if (IS_ERR(priv->reset)) {  in ice40_fpga_probe()
173 		ret = PTR_ERR(priv->reset);  in ice40_fpga_probe()
181 		return -ENOMEM;  in ice40_fpga_probe()
202 	{ .compatible = "lattice,ice40-fpga-mgr", },