Lines Matching +full:clk +full:- +full:mgr
2 * Copyright (c) 2011-2015 Xilinx Inc.
18 #include <linux/clk.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/fpga/fpga-mgr.h>
132 struct clk *clk; member
148 writel(val, priv->io_base + offset); in zynq_fpga_write()
154 return readl(priv->io_base + offset); in zynq_fpga_read()
158 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
174 first = priv->dma_elm == 0; in zynq_step_dma()
175 while (priv->cur_sg) { in zynq_step_dma()
180 addr = sg_dma_address(priv->cur_sg); in zynq_step_dma()
181 len = sg_dma_len(priv->cur_sg); in zynq_step_dma()
182 if (priv->dma_elm + 1 == priv->dma_nelms) { in zynq_step_dma()
189 priv->cur_sg = NULL; in zynq_step_dma()
191 priv->cur_sg = sg_next(priv->cur_sg); in zynq_step_dma()
192 priv->dma_elm++; in zynq_step_dma()
207 if (first && priv->cur_sg) { in zynq_step_dma()
210 } else if (!priv->cur_sg) { in zynq_step_dma()
229 spin_lock(&priv->dma_lock); in zynq_fpga_isr()
232 (intr_status & IXR_DMA_DONE_MASK) && priv->cur_sg) { in zynq_fpga_isr()
235 spin_unlock(&priv->dma_lock); in zynq_fpga_isr()
238 spin_unlock(&priv->dma_lock); in zynq_fpga_isr()
241 complete(&priv->dma_done); in zynq_fpga_isr()
252 for (; count >= 4; buf += 4, count -= 4) in zynq_fpga_has_sync()
259 static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, in zynq_fpga_ops_write_init() argument
267 priv = mgr->priv; in zynq_fpga_ops_write_init()
269 err = clk_enable(priv->clk); in zynq_fpga_ops_write_init()
274 if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) { in zynq_fpga_ops_write_init()
277 dev_err(&mgr->dev, in zynq_fpga_ops_write_init()
279 err = -EINVAL; in zynq_fpga_ops_write_init()
285 if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { in zynq_fpga_ops_write_init()
287 dev_err(&mgr->dev, in zynq_fpga_ops_write_init()
289 err = -EINVAL; in zynq_fpga_ops_write_init()
294 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
298 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
301 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
320 dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n"); in zynq_fpga_ops_write_init()
334 dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n"); in zynq_fpga_ops_write_init()
348 dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n"); in zynq_fpga_ops_write_init()
354 * - enable PCAP interface in zynq_fpga_ops_write_init()
355 * - set throughput for maximum speed (if bistream not crypted) in zynq_fpga_ops_write_init()
356 * - set CPU in user mode in zynq_fpga_ops_write_init()
359 if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) in zynq_fpga_ops_write_init()
373 dev_err(&mgr->dev, "DMA command queue not right\n"); in zynq_fpga_ops_write_init()
374 err = -EBUSY; in zynq_fpga_ops_write_init()
382 clk_disable(priv->clk); in zynq_fpga_ops_write_init()
387 clk_disable(priv->clk); in zynq_fpga_ops_write_init()
392 static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt) in zynq_fpga_ops_write() argument
403 priv = mgr->priv; in zynq_fpga_ops_write()
408 for_each_sg(sgt->sgl, sg, sgt->nents, i) { in zynq_fpga_ops_write()
409 if ((sg->offset % 8) || (sg->length % 4)) { in zynq_fpga_ops_write()
410 dev_err(&mgr->dev, in zynq_fpga_ops_write()
412 return -EINVAL; in zynq_fpga_ops_write()
416 priv->dma_nelms = in zynq_fpga_ops_write()
417 dma_map_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE); in zynq_fpga_ops_write()
418 if (priv->dma_nelms == 0) { in zynq_fpga_ops_write()
419 dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n"); in zynq_fpga_ops_write()
420 return -ENOMEM; in zynq_fpga_ops_write()
424 err = clk_enable(priv->clk); in zynq_fpga_ops_write()
429 reinit_completion(&priv->dma_done); in zynq_fpga_ops_write()
432 spin_lock_irqsave(&priv->dma_lock, flags); in zynq_fpga_ops_write()
433 priv->dma_elm = 0; in zynq_fpga_ops_write()
434 priv->cur_sg = sgt->sgl; in zynq_fpga_ops_write()
436 spin_unlock_irqrestore(&priv->dma_lock, flags); in zynq_fpga_ops_write()
438 timeout = wait_for_completion_timeout(&priv->dma_done, in zynq_fpga_ops_write()
441 spin_lock_irqsave(&priv->dma_lock, flags); in zynq_fpga_ops_write()
443 priv->cur_sg = NULL; in zynq_fpga_ops_write()
444 spin_unlock_irqrestore(&priv->dma_lock, flags); in zynq_fpga_ops_write()
457 err = -EIO; in zynq_fpga_ops_write()
461 if (priv->cur_sg || in zynq_fpga_ops_write()
467 err = -EIO; in zynq_fpga_ops_write()
475 dev_err(&mgr->dev, in zynq_fpga_ops_write()
486 clk_disable(priv->clk); in zynq_fpga_ops_write()
489 dma_unmap_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE); in zynq_fpga_ops_write()
493 static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, in zynq_fpga_ops_write_complete() argument
496 struct zynq_fpga_priv *priv = mgr->priv; in zynq_fpga_ops_write_complete()
500 err = clk_enable(priv->clk); in zynq_fpga_ops_write_complete()
509 clk_disable(priv->clk); in zynq_fpga_ops_write_complete()
515 if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
521 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
528 static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) in zynq_fpga_ops_state() argument
534 priv = mgr->priv; in zynq_fpga_ops_state()
536 err = clk_enable(priv->clk); in zynq_fpga_ops_state()
541 clk_disable(priv->clk); in zynq_fpga_ops_state()
559 struct device *dev = &pdev->dev; in zynq_fpga_probe()
561 struct fpga_manager *mgr; in zynq_fpga_probe() local
567 return -ENOMEM; in zynq_fpga_probe()
568 spin_lock_init(&priv->dma_lock); in zynq_fpga_probe()
571 priv->io_base = devm_ioremap_resource(dev, res); in zynq_fpga_probe()
572 if (IS_ERR(priv->io_base)) in zynq_fpga_probe()
573 return PTR_ERR(priv->io_base); in zynq_fpga_probe()
575 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
577 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
578 dev_err(dev, "unable to get zynq-slcr regmap\n"); in zynq_fpga_probe()
579 return PTR_ERR(priv->slcr); in zynq_fpga_probe()
582 init_completion(&priv->dma_done); in zynq_fpga_probe()
584 priv->irq = platform_get_irq(pdev, 0); in zynq_fpga_probe()
585 if (priv->irq < 0) { in zynq_fpga_probe()
587 return priv->irq; in zynq_fpga_probe()
590 priv->clk = devm_clk_get(dev, "ref_clk"); in zynq_fpga_probe()
591 if (IS_ERR(priv->clk)) { in zynq_fpga_probe()
593 return PTR_ERR(priv->clk); in zynq_fpga_probe()
596 err = clk_prepare_enable(priv->clk); in zynq_fpga_probe()
607 err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev), in zynq_fpga_probe()
611 clk_disable_unprepare(priv->clk); in zynq_fpga_probe()
615 clk_disable(priv->clk); in zynq_fpga_probe()
617 mgr = fpga_mgr_create(dev, "Xilinx Zynq FPGA Manager", in zynq_fpga_probe()
619 if (!mgr) in zynq_fpga_probe()
620 return -ENOMEM; in zynq_fpga_probe()
622 platform_set_drvdata(pdev, mgr); in zynq_fpga_probe()
624 err = fpga_mgr_register(mgr); in zynq_fpga_probe()
627 fpga_mgr_free(mgr); in zynq_fpga_probe()
628 clk_unprepare(priv->clk); in zynq_fpga_probe()
638 struct fpga_manager *mgr; in zynq_fpga_remove() local
640 mgr = platform_get_drvdata(pdev); in zynq_fpga_remove()
641 priv = mgr->priv; in zynq_fpga_remove()
643 fpga_mgr_unregister(mgr); in zynq_fpga_remove()
645 clk_unprepare(priv->clk); in zynq_fpga_remove()
652 { .compatible = "xlnx,zynq-devcfg-1.0", },