Lines Matching +full:port +full:- +full:2
2 * GPIO driver for the ACCES 104-DIO-48E series
6 * it under the terms of the GNU General Public License, version 2, as
14 * This driver supports the following ACCES devices: 104-DIO-48E and
15 * 104-DIO-24E.
38 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
42 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
45 * struct dio48e_gpio - GPIO device private data structure
51 * @base: base port address of the GPIO device
58 unsigned char control[2];
67 const unsigned port = offset / 8; in dio48e_gpio_get_direction() local
70 return !!(dio48egpio->io_state[port] & mask); in dio48e_gpio_get_direction()
78 const unsigned control_addr = dio48egpio->base + 3 + control_port*4; in dio48e_gpio_direction_input()
82 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_direction_input()
84 /* Check if configuring Port C */ in dio48e_gpio_direction_input()
85 if (io_port == 2 || io_port == 5) { in dio48e_gpio_direction_input()
86 /* Port C can be configured by nibble */ in dio48e_gpio_direction_input()
88 dio48egpio->io_state[io_port] |= 0xF0; in dio48e_gpio_direction_input()
89 dio48egpio->control[control_port] |= BIT(3); in dio48e_gpio_direction_input()
91 dio48egpio->io_state[io_port] |= 0x0F; in dio48e_gpio_direction_input()
92 dio48egpio->control[control_port] |= BIT(0); in dio48e_gpio_direction_input()
95 dio48egpio->io_state[io_port] |= 0xFF; in dio48e_gpio_direction_input()
97 dio48egpio->control[control_port] |= BIT(4); in dio48e_gpio_direction_input()
99 dio48egpio->control[control_port] |= BIT(1); in dio48e_gpio_direction_input()
102 control = BIT(7) | dio48egpio->control[control_port]; in dio48e_gpio_direction_input()
107 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_direction_input()
119 const unsigned control_addr = dio48egpio->base + 3 + control_port*4; in dio48e_gpio_direction_output()
120 const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port; in dio48e_gpio_direction_output()
124 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_direction_output()
126 /* Check if configuring Port C */ in dio48e_gpio_direction_output()
127 if (io_port == 2 || io_port == 5) { in dio48e_gpio_direction_output()
128 /* Port C can be configured by nibble */ in dio48e_gpio_direction_output()
130 dio48egpio->io_state[io_port] &= 0x0F; in dio48e_gpio_direction_output()
131 dio48egpio->control[control_port] &= ~BIT(3); in dio48e_gpio_direction_output()
133 dio48egpio->io_state[io_port] &= 0xF0; in dio48e_gpio_direction_output()
134 dio48egpio->control[control_port] &= ~BIT(0); in dio48e_gpio_direction_output()
137 dio48egpio->io_state[io_port] &= 0x00; in dio48e_gpio_direction_output()
139 dio48egpio->control[control_port] &= ~BIT(4); in dio48e_gpio_direction_output()
141 dio48egpio->control[control_port] &= ~BIT(1); in dio48e_gpio_direction_output()
145 dio48egpio->out_state[io_port] |= mask; in dio48e_gpio_direction_output()
147 dio48egpio->out_state[io_port] &= ~mask; in dio48e_gpio_direction_output()
149 control = BIT(7) | dio48egpio->control[control_port]; in dio48e_gpio_direction_output()
152 outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port); in dio48e_gpio_direction_output()
157 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_direction_output()
165 const unsigned port = offset / 8; in dio48e_gpio_get() local
167 const unsigned in_port = (port > 2) ? port + 1 : port; in dio48e_gpio_get()
171 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_get()
174 if (!(dio48egpio->io_state[port] & mask)) { in dio48e_gpio_get()
175 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_get()
176 return -EINVAL; in dio48e_gpio_get()
179 port_state = inb(dio48egpio->base + in_port); in dio48e_gpio_get()
181 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_get()
191 static const size_t ports[] = { 0, 1, 2, 4, 5, 6 }; in dio48e_gpio_get_multiple()
197 const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0); in dio48e_gpio_get_multiple()
201 bitmap_zero(bits, chip->ngpio); in dio48e_gpio_get_multiple()
203 /* get bits are evaluated a gpio port register at a time */ in dio48e_gpio_get_multiple()
217 /* no get bits in this port so skip to next one */ in dio48e_gpio_get_multiple()
221 /* read bits from current gpio port */ in dio48e_gpio_get_multiple()
222 port_state = inb(dio48egpio->base + ports[i]); in dio48e_gpio_get_multiple()
234 const unsigned port = offset / 8; in dio48e_gpio_set() local
236 const unsigned out_port = (port > 2) ? port + 1 : port; in dio48e_gpio_set()
239 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_set()
242 dio48egpio->out_state[port] |= mask; in dio48e_gpio_set()
244 dio48egpio->out_state[port] &= ~mask; in dio48e_gpio_set()
246 outb(dio48egpio->out_state[port], dio48egpio->base + out_port); in dio48e_gpio_set()
248 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_set()
257 unsigned int port; in dio48e_gpio_set_multiple() local
263 for (i = 0; i < chip->ngpio; i += gpio_reg_size) { in dio48e_gpio_set_multiple()
266 i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size; in dio48e_gpio_set_multiple()
270 port = i / gpio_reg_size; in dio48e_gpio_set_multiple()
271 out_port = (port > 2) ? port + 1 : port; in dio48e_gpio_set_multiple()
274 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_set_multiple()
277 dio48egpio->out_state[port] &= ~mask[BIT_WORD(i)]; in dio48e_gpio_set_multiple()
278 dio48egpio->out_state[port] |= bitmask; in dio48e_gpio_set_multiple()
279 outb(dio48egpio->out_state[port], dio48egpio->base + out_port); in dio48e_gpio_set_multiple()
281 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_set_multiple()
300 /* only bit 3 on each respective Port C supports interrupts */ in dio48e_irq_mask()
304 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_irq_mask()
307 dio48egpio->irq_mask &= ~BIT(0); in dio48e_irq_mask()
309 dio48egpio->irq_mask &= ~BIT(1); in dio48e_irq_mask()
311 if (!dio48egpio->irq_mask) in dio48e_irq_mask()
313 inb(dio48egpio->base + 0xB); in dio48e_irq_mask()
315 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_irq_mask()
325 /* only bit 3 on each respective Port C supports interrupts */ in dio48e_irq_unmask()
329 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_irq_unmask()
331 if (!dio48egpio->irq_mask) { in dio48e_irq_unmask()
333 outb(0x00, dio48egpio->base + 0xF); in dio48e_irq_unmask()
334 outb(0x00, dio48egpio->base + 0xB); in dio48e_irq_unmask()
338 dio48egpio->irq_mask |= BIT(0); in dio48e_irq_unmask()
340 dio48egpio->irq_mask |= BIT(1); in dio48e_irq_unmask()
342 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_irq_unmask()
349 /* only bit 3 on each respective Port C supports interrupts */ in dio48e_irq_set_type()
351 return -EINVAL; in dio48e_irq_set_type()
354 return -EINVAL; in dio48e_irq_set_type()
360 .name = "104-dio-48e",
370 struct gpio_chip *const chip = &dio48egpio->chip; in dio48e_irq_handler()
371 const unsigned long irq_mask = dio48egpio->irq_mask; in dio48e_irq_handler()
374 for_each_set_bit(gpio, &irq_mask, 2) in dio48e_irq_handler()
375 generic_handle_irq(irq_find_mapping(chip->irq.domain, in dio48e_irq_handler()
378 raw_spin_lock(&dio48egpio->lock); in dio48e_irq_handler()
380 outb(0x00, dio48egpio->base + 0xF); in dio48e_irq_handler()
382 raw_spin_unlock(&dio48egpio->lock); in dio48e_irq_handler()
389 "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
390 "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
391 "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
392 "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
393 "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
394 "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
395 "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
396 "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
397 "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
398 "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
399 "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
400 "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
401 "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
402 "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
403 "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
404 "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
415 return -ENOMEM; in dio48e_probe()
418 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", in dio48e_probe()
420 return -EBUSY; in dio48e_probe()
423 dio48egpio->chip.label = name; in dio48e_probe()
424 dio48egpio->chip.parent = dev; in dio48e_probe()
425 dio48egpio->chip.owner = THIS_MODULE; in dio48e_probe()
426 dio48egpio->chip.base = -1; in dio48e_probe()
427 dio48egpio->chip.ngpio = DIO48E_NGPIO; in dio48e_probe()
428 dio48egpio->chip.names = dio48e_names; in dio48e_probe()
429 dio48egpio->chip.get_direction = dio48e_gpio_get_direction; in dio48e_probe()
430 dio48egpio->chip.direction_input = dio48e_gpio_direction_input; in dio48e_probe()
431 dio48egpio->chip.direction_output = dio48e_gpio_direction_output; in dio48e_probe()
432 dio48egpio->chip.get = dio48e_gpio_get; in dio48e_probe()
433 dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple; in dio48e_probe()
434 dio48egpio->chip.set = dio48e_gpio_set; in dio48e_probe()
435 dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple; in dio48e_probe()
436 dio48egpio->base = base[id]; in dio48e_probe()
438 raw_spin_lock_init(&dio48egpio->lock); in dio48e_probe()
440 err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio); in dio48e_probe()
450 outb(0x00, base[id] + 2); in dio48e_probe()
461 err = gpiochip_irqchip_add(&dio48egpio->chip, &dio48e_irqchip, 0, in dio48e_probe()
481 .name = "104-dio-48e"
487 MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");