Lines Matching +full:lock +full:- +full:offset
47 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
59 spinlock_t lock; member
217 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
219 return gpio->base + bank->rdata_reg; in bank_reg()
221 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
223 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
225 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
227 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
229 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
231 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
233 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; in bank_reg()
235 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; in bank_reg()
237 return gpio->base + bank->tolerance_regs; in bank_reg()
239 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; in bank_reg()
241 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; in bank_reg()
254 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) in to_bank() argument
256 unsigned int bank = GPIO_BANK(offset); in to_bank()
264 return !(props->input || props->output); in is_bank_props_sentinel()
268 struct aspeed_gpio *gpio, unsigned int offset) in find_bank_props() argument
270 const struct aspeed_bank_props *props = gpio->config->props; in find_bank_props()
273 if (props->bank == GPIO_BANK(offset)) in find_bank_props()
281 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) in have_gpio() argument
283 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_gpio()
284 const struct aspeed_gpio_bank *bank = to_bank(offset); in have_gpio()
285 unsigned int group = GPIO_OFFSET(offset) / 8; in have_gpio()
287 return bank->names[group][0] != '\0' && in have_gpio()
288 (!props || ((props->input | props->output) & GPIO_BIT(offset))); in have_gpio()
291 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) in have_input() argument
293 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_input()
295 return !props || (props->input & GPIO_BIT(offset)); in have_input()
301 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) in have_output() argument
303 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_output()
305 return !props || (props->output & GPIO_BIT(offset)); in have_output()
341 unsigned int offset) in aspeed_gpio_copro_request() argument
343 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_request()
345 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_gpio_copro_request()
347 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_gpio_copro_request()
349 if (!copro_ops->request_access) in aspeed_gpio_copro_request()
353 copro_ops->request_access(copro_data); in aspeed_gpio_copro_request()
356 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM); in aspeed_gpio_copro_request()
359 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); in aspeed_gpio_copro_request()
365 unsigned int offset) in aspeed_gpio_copro_release() argument
367 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_release()
369 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_gpio_copro_release()
371 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_gpio_copro_release()
373 if (!copro_ops->release_access) in aspeed_gpio_copro_release()
377 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, in aspeed_gpio_copro_release()
381 copro_ops->release_access(copro_data); in aspeed_gpio_copro_release()
384 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) in aspeed_gpio_get() argument
387 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_get()
389 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); in aspeed_gpio_get()
392 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, in __aspeed_gpio_set() argument
396 const struct aspeed_gpio_bank *bank = to_bank(offset); in __aspeed_gpio_set()
401 reg = gpio->dcache[GPIO_BANK(offset)]; in __aspeed_gpio_set()
404 reg |= GPIO_BIT(offset); in __aspeed_gpio_set()
406 reg &= ~GPIO_BIT(offset); in __aspeed_gpio_set()
407 gpio->dcache[GPIO_BANK(offset)] = reg; in __aspeed_gpio_set()
412 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, in aspeed_gpio_set() argument
419 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set()
420 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set()
422 __aspeed_gpio_set(gc, offset, val); in aspeed_gpio_set()
425 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set()
426 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set()
429 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) in aspeed_gpio_dir_in() argument
432 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_dir_in()
438 if (!have_input(gpio, offset)) in aspeed_gpio_dir_in()
439 return -ENOTSUPP; in aspeed_gpio_dir_in()
441 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_in()
444 reg &= ~GPIO_BIT(offset); in aspeed_gpio_dir_in()
446 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_in()
449 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_in()
451 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_in()
457 unsigned int offset, int val) in aspeed_gpio_dir_out() argument
460 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_dir_out()
466 if (!have_output(gpio, offset)) in aspeed_gpio_dir_out()
467 return -ENOTSUPP; in aspeed_gpio_dir_out()
469 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_out()
472 reg |= GPIO_BIT(offset); in aspeed_gpio_dir_out()
474 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_out()
475 __aspeed_gpio_set(gc, offset, val); in aspeed_gpio_dir_out()
479 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_out()
480 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_out()
485 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) in aspeed_gpio_get_direction() argument
488 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_get_direction()
492 if (!have_input(gpio, offset)) in aspeed_gpio_get_direction()
495 if (!have_output(gpio, offset)) in aspeed_gpio_get_direction()
498 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_get_direction()
500 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); in aspeed_gpio_get_direction()
502 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_get_direction()
511 u32 *bit, int *offset) in irqd_to_aspeed_gpio_data() argument
515 *offset = irqd_to_hwirq(d); in irqd_to_aspeed_gpio_data()
520 if (!have_irq(internal, *offset)) in irqd_to_aspeed_gpio_data()
521 return -ENOTSUPP; in irqd_to_aspeed_gpio_data()
524 *bank = to_bank(*offset); in irqd_to_aspeed_gpio_data()
525 *bit = GPIO_BIT(*offset); in irqd_to_aspeed_gpio_data()
536 int rc, offset; in aspeed_gpio_irq_ack() local
540 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_ack()
546 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_ack()
547 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_ack()
552 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_ack()
553 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_ack()
563 int rc, offset; in aspeed_gpio_irq_set_mask() local
566 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_set_mask()
572 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
573 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_set_mask()
583 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_set_mask()
584 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
608 int rc, offset; in aspeed_gpio_set_type() local
611 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_set_type()
613 return -EINVAL; in aspeed_gpio_set_type()
633 return -EINVAL; in aspeed_gpio_set_type()
636 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set_type()
637 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set_type()
655 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set_type()
656 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set_type()
679 girq = irq_find_mapping(gc->irq.domain, i * 32 + p); in aspeed_gpio_irq_handler()
689 .name = "aspeed-gpio",
698 const struct aspeed_bank_props *props = gpio->config->props; in set_irq_valid_mask()
701 unsigned int offset; in set_irq_valid_mask() local
702 const unsigned long int input = props->input; in set_irq_valid_mask()
705 for_each_clear_bit(offset, &input, 32) { in set_irq_valid_mask()
706 unsigned int i = props->bank * 32 + offset; in set_irq_valid_mask()
708 if (i >= gpio->config->nr_gpios) in set_irq_valid_mask()
711 clear_bit(i, gpio->chip.irq.valid_mask); in set_irq_valid_mask()
727 gpio->irq = rc; in aspeed_gpio_setup_irqs()
731 rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip, in aspeed_gpio_setup_irqs()
734 dev_info(&pdev->dev, "Could not add irqchip\n"); in aspeed_gpio_setup_irqs()
738 gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip, in aspeed_gpio_setup_irqs()
739 gpio->irq, aspeed_gpio_irq_handler); in aspeed_gpio_setup_irqs()
745 unsigned int offset, bool enable) in aspeed_gpio_reset_tolerance() argument
753 treg = bank_reg(gpio, to_bank(offset), reg_tolerance); in aspeed_gpio_reset_tolerance()
755 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
756 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_reset_tolerance()
761 val |= GPIO_BIT(offset); in aspeed_gpio_reset_tolerance()
763 val &= ~GPIO_BIT(offset); in aspeed_gpio_reset_tolerance()
768 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_reset_tolerance()
769 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
774 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) in aspeed_gpio_request() argument
776 if (!have_gpio(gpiochip_get_data(chip), offset)) in aspeed_gpio_request()
777 return -ENODEV; in aspeed_gpio_request()
779 return pinctrl_gpio_request(chip->base + offset); in aspeed_gpio_request()
782 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) in aspeed_gpio_free() argument
784 pinctrl_gpio_free(chip->base + offset); in aspeed_gpio_free()
794 rate = clk_get_rate(gpio->clk); in usecs_to_cycles()
796 return -ENOTSUPP; in usecs_to_cycles()
802 return -ERANGE; in usecs_to_cycles()
810 /* Call under gpio->lock */
812 unsigned int offset, unsigned int timer) in register_allocated_timer() argument
814 if (WARN(gpio->offset_timer[offset] != 0, in register_allocated_timer()
815 "Offset %d already allocated timer %d\n", in register_allocated_timer()
816 offset, gpio->offset_timer[offset])) in register_allocated_timer()
817 return -EINVAL; in register_allocated_timer()
819 if (WARN(gpio->timer_users[timer] == UINT_MAX, in register_allocated_timer()
821 return -EPERM; in register_allocated_timer()
823 gpio->offset_timer[offset] = timer; in register_allocated_timer()
824 gpio->timer_users[timer]++; in register_allocated_timer()
829 /* Call under gpio->lock */
831 unsigned int offset) in unregister_allocated_timer() argument
833 if (WARN(gpio->offset_timer[offset] == 0, in unregister_allocated_timer()
834 "No timer allocated to offset %d\n", offset)) in unregister_allocated_timer()
835 return -EINVAL; in unregister_allocated_timer()
837 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, in unregister_allocated_timer()
839 gpio->offset_timer[offset])) in unregister_allocated_timer()
840 return -EINVAL; in unregister_allocated_timer()
842 gpio->timer_users[gpio->offset_timer[offset]]--; in unregister_allocated_timer()
843 gpio->offset_timer[offset] = 0; in unregister_allocated_timer()
848 /* Call under gpio->lock */
850 unsigned int offset) in timer_allocation_registered() argument
852 return gpio->offset_timer[offset] > 0; in timer_allocation_registered()
855 /* Call under gpio->lock */
856 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, in configure_timer() argument
859 const struct aspeed_gpio_bank *bank = to_bank(offset); in configure_timer()
860 const u32 mask = GPIO_BIT(offset); in configure_timer()
869 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); in configure_timer()
873 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); in configure_timer()
876 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, in enable_debounce() argument
885 if (!gpio->clk) in enable_debounce()
886 return -EINVAL; in enable_debounce()
890 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", in enable_debounce()
891 usecs, clk_get_rate(gpio->clk), rc); in enable_debounce()
895 spin_lock_irqsave(&gpio->lock, flags); in enable_debounce()
897 if (timer_allocation_registered(gpio, offset)) { in enable_debounce()
898 rc = unregister_allocated_timer(gpio, offset); in enable_debounce()
907 cycles = ioread32(gpio->base + debounce_timers[i]); in enable_debounce()
919 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { in enable_debounce()
920 if (gpio->timer_users[j] == 0) in enable_debounce()
924 if (j == ARRAY_SIZE(gpio->timer_users)) { in enable_debounce()
925 dev_warn(chip->parent, in enable_debounce()
929 rc = -EPERM; in enable_debounce()
932 * We already adjusted the accounting to remove @offset in enable_debounce()
934 * the hardware so @offset has timers disabled for in enable_debounce()
937 configure_timer(gpio, offset, 0); in enable_debounce()
943 iowrite32(requested_cycles, gpio->base + debounce_timers[i]); in enable_debounce()
947 rc = -EINVAL; in enable_debounce()
951 register_allocated_timer(gpio, offset, i); in enable_debounce()
952 configure_timer(gpio, offset, i); in enable_debounce()
955 spin_unlock_irqrestore(&gpio->lock, flags); in enable_debounce()
960 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) in disable_debounce() argument
966 spin_lock_irqsave(&gpio->lock, flags); in disable_debounce()
968 rc = unregister_allocated_timer(gpio, offset); in disable_debounce()
970 configure_timer(gpio, offset, 0); in disable_debounce()
972 spin_unlock_irqrestore(&gpio->lock, flags); in disable_debounce()
977 static int set_debounce(struct gpio_chip *chip, unsigned int offset, in set_debounce() argument
982 if (!have_debounce(gpio, offset)) in set_debounce()
983 return -ENOTSUPP; in set_debounce()
986 return enable_debounce(chip, offset, usecs); in set_debounce()
988 return disable_debounce(chip, offset); in set_debounce()
991 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, in aspeed_gpio_set_config() argument
998 return set_debounce(chip, offset, arg); in aspeed_gpio_set_config()
1002 return pinctrl_gpio_set_config(offset, config); in aspeed_gpio_set_config()
1005 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ in aspeed_gpio_set_config()
1006 return -ENOTSUPP; in aspeed_gpio_set_config()
1008 return aspeed_gpio_reset_tolerance(chip, offset, arg); in aspeed_gpio_set_config()
1010 return -ENOTSUPP; in aspeed_gpio_set_config()
1014 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handhsaking with
1029 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
1033 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
1034 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
1035 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
1042 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); in aspeed_gpio_copro_grab_gpio() local
1043 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_grab_gpio()
1046 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
1047 gpio->cf_copro_bankmap = kzalloc(gpio->config->nr_gpios >> 3, GFP_KERNEL); in aspeed_gpio_copro_grab_gpio()
1048 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
1049 return -ENOMEM; in aspeed_gpio_copro_grab_gpio()
1050 if (offset < 0 || offset > gpio->config->nr_gpios) in aspeed_gpio_copro_grab_gpio()
1051 return -EINVAL; in aspeed_gpio_copro_grab_gpio()
1052 bindex = offset >> 3; in aspeed_gpio_copro_grab_gpio()
1054 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1057 if (gpio->cf_copro_bankmap[bindex] == 0xff) { in aspeed_gpio_copro_grab_gpio()
1058 rc = -EIO; in aspeed_gpio_copro_grab_gpio()
1061 gpio->cf_copro_bankmap[bindex]++; in aspeed_gpio_copro_grab_gpio()
1064 if (gpio->cf_copro_bankmap[bindex] == 1) in aspeed_gpio_copro_grab_gpio()
1069 *vreg_offset = bank->val_regs; in aspeed_gpio_copro_grab_gpio()
1071 *dreg_offset = bank->rdata_reg; in aspeed_gpio_copro_grab_gpio()
1073 *bit = GPIO_OFFSET(offset); in aspeed_gpio_copro_grab_gpio()
1075 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1081 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1088 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); in aspeed_gpio_copro_release_gpio() local
1089 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_release_gpio()
1092 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_release_gpio()
1093 return -ENXIO; in aspeed_gpio_copro_release_gpio()
1095 if (offset < 0 || offset > gpio->config->nr_gpios) in aspeed_gpio_copro_release_gpio()
1096 return -EINVAL; in aspeed_gpio_copro_release_gpio()
1097 bindex = offset >> 3; in aspeed_gpio_copro_release_gpio()
1099 spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1102 if (gpio->cf_copro_bankmap[bindex] == 0) { in aspeed_gpio_copro_release_gpio()
1103 rc = -EIO; in aspeed_gpio_copro_release_gpio()
1106 gpio->cf_copro_bankmap[bindex]--; in aspeed_gpio_copro_release_gpio()
1109 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1113 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1128 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1133 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1139 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1145 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1149 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1150 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1162 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_gpio_probe()
1164 return -ENOMEM; in aspeed_gpio_probe()
1167 gpio->base = devm_ioremap_resource(&pdev->dev, res); in aspeed_gpio_probe()
1168 if (IS_ERR(gpio->base)) in aspeed_gpio_probe()
1169 return PTR_ERR(gpio->base); in aspeed_gpio_probe()
1171 spin_lock_init(&gpio->lock); in aspeed_gpio_probe()
1173 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); in aspeed_gpio_probe()
1175 return -EINVAL; in aspeed_gpio_probe()
1177 gpio->clk = of_clk_get(pdev->dev.of_node, 0); in aspeed_gpio_probe()
1178 if (IS_ERR(gpio->clk)) { in aspeed_gpio_probe()
1179 dev_warn(&pdev->dev, in aspeed_gpio_probe()
1181 gpio->clk = NULL; in aspeed_gpio_probe()
1184 gpio->config = gpio_id->data; in aspeed_gpio_probe()
1186 gpio->chip.parent = &pdev->dev; in aspeed_gpio_probe()
1187 gpio->chip.ngpio = gpio->config->nr_gpios; in aspeed_gpio_probe()
1188 gpio->chip.parent = &pdev->dev; in aspeed_gpio_probe()
1189 gpio->chip.direction_input = aspeed_gpio_dir_in; in aspeed_gpio_probe()
1190 gpio->chip.direction_output = aspeed_gpio_dir_out; in aspeed_gpio_probe()
1191 gpio->chip.get_direction = aspeed_gpio_get_direction; in aspeed_gpio_probe()
1192 gpio->chip.request = aspeed_gpio_request; in aspeed_gpio_probe()
1193 gpio->chip.free = aspeed_gpio_free; in aspeed_gpio_probe()
1194 gpio->chip.get = aspeed_gpio_get; in aspeed_gpio_probe()
1195 gpio->chip.set = aspeed_gpio_set; in aspeed_gpio_probe()
1196 gpio->chip.set_config = aspeed_gpio_set_config; in aspeed_gpio_probe()
1197 gpio->chip.label = dev_name(&pdev->dev); in aspeed_gpio_probe()
1198 gpio->chip.base = -1; in aspeed_gpio_probe()
1199 gpio->chip.irq.need_valid_mask = true; in aspeed_gpio_probe()
1202 banks = DIV_ROUND_UP(gpio->config->nr_gpios, 32); in aspeed_gpio_probe()
1203 gpio->dcache = devm_kcalloc(&pdev->dev, in aspeed_gpio_probe()
1205 if (!gpio->dcache) in aspeed_gpio_probe()
1206 return -ENOMEM; in aspeed_gpio_probe()
1215 gpio->dcache[i] = ioread32(addr); in aspeed_gpio_probe()
1222 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_gpio_probe()
1226 gpio->offset_timer = in aspeed_gpio_probe()
1227 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); in aspeed_gpio_probe()
1228 if (!gpio->offset_timer) in aspeed_gpio_probe()
1229 return -ENOMEM; in aspeed_gpio_probe()