Lines Matching +full:irq +full:- +full:gpios
4 * Copyright (c) 2006-2007 David Brownell
18 #include <linux/irq.h>
25 #include <linux/platform_data/gpio-davinci.h>
41 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
60 /*--------------------------------------------------------------------------*/
73 g = d->regs[bank]; in __davinci_direction()
74 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
75 temp = readl_relaxed(&g->dir); in __davinci_direction()
78 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
82 writel_relaxed(temp, &g->dir); in __davinci_direction()
83 spin_unlock_irqrestore(&d->lock, flags); in __davinci_direction()
112 g = d->regs[bank]; in davinci_gpio_get()
114 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); in davinci_gpio_get()
127 g = d->regs[bank]; in davinci_gpio_set()
130 value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
136 struct device_node *dn = pdev->dev.of_node; in davinci_gpio_get_pdata()
141 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) in davinci_gpio_get_pdata()
142 return dev_get_platdata(&pdev->dev); in davinci_gpio_get_pdata()
144 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in davinci_gpio_get_pdata()
152 pdata->ngpio = val; in davinci_gpio_get_pdata()
154 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); in davinci_gpio_get_pdata()
158 pdata->gpio_unbanked = val; in davinci_gpio_get_pdata()
163 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); in davinci_gpio_get_pdata()
174 struct device *dev = &pdev->dev; in davinci_gpio_probe()
181 return -EINVAL; in davinci_gpio_probe()
184 dev->platform_data = pdata; in davinci_gpio_probe()
188 * and "ngpio" is one more than the largest zero-based in davinci_gpio_probe()
191 ngpio = pdata->ngpio; in davinci_gpio_probe()
193 dev_err(dev, "How many GPIOs?\n"); in davinci_gpio_probe()
194 return -EINVAL; in davinci_gpio_probe()
202 * interrupts is equal to number of gpios else all are banked so in davinci_gpio_probe()
203 * number of interrupts is equal to number of banks(each with 16 gpios) in davinci_gpio_probe()
205 if (pdata->gpio_unbanked) in davinci_gpio_probe()
206 nirq = pdata->gpio_unbanked; in davinci_gpio_probe()
215 return -ENOMEM; in davinci_gpio_probe()
223 chips->irqs[i] = platform_get_irq(pdev, i); in davinci_gpio_probe()
224 if (chips->irqs[i] < 0) { in davinci_gpio_probe()
225 if (chips->irqs[i] != -EPROBE_DEFER) in davinci_gpio_probe()
226 dev_info(dev, "IRQ not populated, err = %d\n", in davinci_gpio_probe()
227 chips->irqs[i]); in davinci_gpio_probe()
228 return chips->irqs[i]; in davinci_gpio_probe()
233 chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL); in davinci_gpio_probe()
234 if (!chips->chip.label) in davinci_gpio_probe()
235 return -ENOMEM; in davinci_gpio_probe()
237 chips->chip.direction_input = davinci_direction_in; in davinci_gpio_probe()
238 chips->chip.get = davinci_gpio_get; in davinci_gpio_probe()
239 chips->chip.direction_output = davinci_direction_out; in davinci_gpio_probe()
240 chips->chip.set = davinci_gpio_set; in davinci_gpio_probe()
242 chips->chip.ngpio = ngpio; in davinci_gpio_probe()
243 chips->chip.base = bank_base; in davinci_gpio_probe()
246 chips->chip.of_gpio_n_cells = 2; in davinci_gpio_probe()
247 chips->chip.parent = dev; in davinci_gpio_probe()
248 chips->chip.of_node = dev->of_node; in davinci_gpio_probe()
250 if (of_property_read_bool(dev->of_node, "gpio-ranges")) { in davinci_gpio_probe()
251 chips->chip.request = gpiochip_generic_request; in davinci_gpio_probe()
252 chips->chip.free = gpiochip_generic_free; in davinci_gpio_probe()
255 spin_lock_init(&chips->lock); in davinci_gpio_probe()
259 chips->regs[bank] = gpio_base + offset_array[bank]; in davinci_gpio_probe()
261 ret = devm_gpiochip_add_data(dev, &chips->chip, chips); in davinci_gpio_probe()
274 ctrl_num--; in davinci_gpio_probe()
275 bank_base -= ngpio; in davinci_gpio_probe()
280 /*--------------------------------------------------------------------------*/
285 * NOTE: The first few GPIOs also have direct INTC hookups in addition
286 * to their GPIOBNK0 irq, with a bit less overhead.
288 * All those INTC hookups (direct, plus several IRQ banks) can also
297 writel_relaxed(mask, &g->clr_falling); in gpio_irq_disable()
298 writel_relaxed(mask, &g->clr_rising); in gpio_irq_disable()
312 writel_relaxed(mask, &g->set_falling); in gpio_irq_enable()
314 writel_relaxed(mask, &g->set_rising); in gpio_irq_enable()
320 return -EINVAL; in gpio_irq_type()
342 bank_num = irqdata->bank_num; in gpio_irq_handler()
343 g = irqdata->regs; in gpio_irq_handler()
344 d = irqdata->chip; in gpio_irq_handler()
350 /* temporarily mask (level sensitive) parent IRQ */ in gpio_irq_handler()
358 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
361 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
368 /* Max number of gpios per controller is 144 so in gpio_irq_handler()
374 irq_find_mapping(d->irq_domain, hw_irq)); in gpio_irq_handler()
378 /* now it may re-trigger */ in gpio_irq_handler()
385 if (d->irq_domain) in gpio_to_irq_banked()
386 return irq_create_mapping(d->irq_domain, offset); in gpio_to_irq_banked()
388 return -ENXIO; in gpio_to_irq_banked()
397 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). in gpio_to_irq_unbanked()
399 if (offset < d->gpio_unbanked) in gpio_to_irq_unbanked()
400 return d->irqs[offset]; in gpio_to_irq_unbanked()
402 return -ENODEV; in gpio_to_irq_unbanked()
412 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; in gpio_irq_type_unbanked()
414 if (data->irq == d->irqs[i]) in gpio_irq_type_unbanked()
418 return -EINVAL; in gpio_irq_type_unbanked()
423 return -EINVAL; in gpio_irq_type_unbanked()
426 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
428 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
434 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, in davinci_gpio_irq_map() argument
438 (struct davinci_gpio_controller *)d->host_data; in davinci_gpio_irq_map()
439 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; in davinci_gpio_irq_map()
441 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, in davinci_gpio_irq_map()
443 irq_set_irq_type(irq, IRQ_TYPE_NONE); in davinci_gpio_irq_map()
444 irq_set_chip_data(irq, (__force void *)g); in davinci_gpio_irq_map()
445 irq_set_handler_data(irq, (void *)__gpio_mask(hw)); in davinci_gpio_irq_map()
455 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) in davinci_gpio_get_irq_chip() argument
459 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); in davinci_gpio_get_irq_chip()
464 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) in keystone_gpio_get_irq_chip() argument
468 gpio_unbanked = *irq_get_chip(irq); in keystone_gpio_get_irq_chip()
477 * calls ... so if no gpios are wakeup events the clock can be disabled,
485 int irq; in davinci_gpio_irq_setup() local
490 struct device *dev = &pdev->dev; in davinci_gpio_irq_setup()
492 struct davinci_gpio_platform_data *pdata = dev->platform_data; in davinci_gpio_irq_setup()
507 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; in davinci_gpio_irq_setup()
509 ngpio = pdata->ngpio; in davinci_gpio_irq_setup()
521 if (!pdata->gpio_unbanked) { in davinci_gpio_irq_setup()
522 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); in davinci_gpio_irq_setup()
523 if (irq < 0) { in davinci_gpio_irq_setup()
524 dev_err(dev, "Couldn't allocate IRQ numbers\n"); in davinci_gpio_irq_setup()
526 return irq; in davinci_gpio_irq_setup()
529 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, in davinci_gpio_irq_setup()
533 dev_err(dev, "Couldn't register an IRQ domain\n"); in davinci_gpio_irq_setup()
535 return -ENODEV; in davinci_gpio_irq_setup()
541 * banked IRQs. Having GPIOs in the first GPIO bank use direct in davinci_gpio_irq_setup()
545 chips->chip.to_irq = gpio_to_irq_banked; in davinci_gpio_irq_setup()
546 chips->irq_domain = irq_domain; in davinci_gpio_irq_setup()
549 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO in davinci_gpio_irq_setup()
551 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. in davinci_gpio_irq_setup()
553 if (pdata->gpio_unbanked) { in davinci_gpio_irq_setup()
555 chips->chip.to_irq = gpio_to_irq_unbanked; in davinci_gpio_irq_setup()
556 chips->gpio_unbanked = pdata->gpio_unbanked; in davinci_gpio_irq_setup()
557 binten = GENMASK(pdata->gpio_unbanked / 16, 0); in davinci_gpio_irq_setup()
560 irq = chips->irqs[0]; in davinci_gpio_irq_setup()
561 irq_chip = gpio_get_irq_chip(irq); in davinci_gpio_irq_setup()
562 irq_chip->name = "GPIO-AINTC"; in davinci_gpio_irq_setup()
563 irq_chip->irq_set_type = gpio_irq_type_unbanked; in davinci_gpio_irq_setup()
566 g = chips->regs[0]; in davinci_gpio_irq_setup()
567 writel_relaxed(~0, &g->set_falling); in davinci_gpio_irq_setup()
568 writel_relaxed(~0, &g->set_rising); in davinci_gpio_irq_setup()
571 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { in davinci_gpio_irq_setup()
572 irq_set_chip(chips->irqs[gpio], irq_chip); in davinci_gpio_irq_setup()
573 irq_set_handler_data(chips->irqs[gpio], chips); in davinci_gpio_irq_setup()
574 irq_set_status_flags(chips->irqs[gpio], in davinci_gpio_irq_setup()
587 * There are register sets for 32 GPIOs. 2 banks of 16 in davinci_gpio_irq_setup()
588 * GPIOs are covered by each set of registers hence divide by 2 in davinci_gpio_irq_setup()
590 g = chips->regs[bank / 2]; in davinci_gpio_irq_setup()
591 writel_relaxed(~0, &g->clr_falling); in davinci_gpio_irq_setup()
592 writel_relaxed(~0, &g->clr_rising); in davinci_gpio_irq_setup()
595 * Each chip handles 32 gpios, and each irq bank consists of 16 in davinci_gpio_irq_setup()
596 * gpio irqs. Pass the irq bank's corresponding controller to in davinci_gpio_irq_setup()
597 * the chained irq handler. in davinci_gpio_irq_setup()
599 irqdata = devm_kzalloc(&pdev->dev, in davinci_gpio_irq_setup()
605 return -ENOMEM; in davinci_gpio_irq_setup()
608 irqdata->regs = g; in davinci_gpio_irq_setup()
609 irqdata->bank_num = bank; in davinci_gpio_irq_setup()
610 irqdata->chip = chips; in davinci_gpio_irq_setup()
612 irq_set_chained_handler_and_data(chips->irqs[bank], in davinci_gpio_irq_setup()
620 * BINTEN -- per-bank interrupt enable. genirq would also let these in davinci_gpio_irq_setup()
629 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
630 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},