Lines Matching +full:gpio +full:- +full:out +full:- +full:pol
6 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
12 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
30 #include <linux/gpio/driver.h>
33 #include <linux/gpio/driver.h>
50 /* Structure for an irq of the core - called an underlying irq */
53 u8 uirq; /* Underlying irq of the gpio driver */
57 * Structure for an irq of a gpio line handed out by this driver. The index is
61 s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
62 u8 irq; /* irq for the gpio line */
73 * The grgpio core can have multiple "underlying" irqs. The gpio lines
76 * hands out separate irqs to each gpio line
87 * This array contains information for each gpio line on the irqs
88 * obtains from this driver. An index value of -1 for a certain gpio
98 struct gpio_chip *gc = &priv->gc; in grgpio_set_imask()
101 priv->imask |= BIT(offset); in grgpio_set_imask()
103 priv->imask &= ~BIT(offset); in grgpio_set_imask()
104 gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); in grgpio_set_imask()
111 if (offset >= gc->ngpio) in grgpio_to_irq()
112 return -ENXIO; in grgpio_to_irq()
114 if (priv->lirqs[offset].index < 0) in grgpio_to_irq()
115 return -ENXIO; in grgpio_to_irq()
117 return irq_create_mapping(priv->domain, offset); in grgpio_to_irq()
120 /* -------------------- IRQ chip functions -------------------- */
126 u32 mask = BIT(d->hwirq); in grgpio_irq_set_type()
129 u32 pol; in grgpio_irq_set_type() local
134 pol = 0; in grgpio_irq_set_type()
138 pol = mask; in grgpio_irq_set_type()
142 pol = 0; in grgpio_irq_set_type()
146 pol = mask; in grgpio_irq_set_type()
150 return -EINVAL; in grgpio_irq_set_type()
153 spin_lock_irqsave(&priv->gc.bgpio_lock, flags); in grgpio_irq_set_type()
155 ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask; in grgpio_irq_set_type()
156 iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask; in grgpio_irq_set_type()
158 priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol); in grgpio_irq_set_type()
159 priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge); in grgpio_irq_set_type()
161 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); in grgpio_irq_set_type()
169 int offset = d->hwirq; in grgpio_irq_mask()
172 spin_lock_irqsave(&priv->gc.bgpio_lock, flags); in grgpio_irq_mask()
176 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); in grgpio_irq_mask()
182 int offset = d->hwirq; in grgpio_irq_unmask()
185 spin_lock_irqsave(&priv->gc.bgpio_lock, flags); in grgpio_irq_unmask()
189 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); in grgpio_irq_unmask()
202 int ngpio = priv->gc.ngpio; in grgpio_irq_handler()
207 spin_lock_irqsave(&priv->gc.bgpio_lock, flags); in grgpio_irq_handler()
210 * For each gpio line, call its interrupt handler if it its underlying in grgpio_irq_handler()
214 struct grgpio_lirq *lirq = &priv->lirqs[i]; in grgpio_irq_handler()
216 if (priv->imask & BIT(i) && lirq->index >= 0 && in grgpio_irq_handler()
217 priv->uirqs[lirq->index].uirq == irq) { in grgpio_irq_handler()
218 generic_handle_irq(lirq->irq); in grgpio_irq_handler()
223 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); in grgpio_irq_handler()
226 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq); in grgpio_irq_handler()
238 struct grgpio_priv *priv = d->host_data; in grgpio_irq_map()
246 return -EINVAL; in grgpio_irq_map()
248 lirq = &priv->lirqs[offset]; in grgpio_irq_map()
249 if (lirq->index < 0) in grgpio_irq_map()
250 return -EINVAL; in grgpio_irq_map()
252 dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n", in grgpio_irq_map()
255 spin_lock_irqsave(&priv->gc.bgpio_lock, flags); in grgpio_irq_map()
258 lirq->irq = irq; in grgpio_irq_map()
259 uirq = &priv->uirqs[lirq->index]; in grgpio_irq_map()
260 if (uirq->refcnt == 0) { in grgpio_irq_map()
261 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); in grgpio_irq_map()
262 ret = request_irq(uirq->uirq, grgpio_irq_handler, 0, in grgpio_irq_map()
263 dev_name(priv->dev), priv); in grgpio_irq_map()
265 dev_err(priv->dev, in grgpio_irq_map()
267 uirq->uirq); in grgpio_irq_map()
270 spin_lock_irqsave(&priv->gc.bgpio_lock, flags); in grgpio_irq_map()
272 uirq->refcnt++; in grgpio_irq_map()
274 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); in grgpio_irq_map()
287 struct grgpio_priv *priv = d->host_data; in grgpio_irq_unmap()
292 int ngpio = priv->gc.ngpio; in grgpio_irq_unmap()
298 spin_lock_irqsave(&priv->gc.bgpio_lock, flags); in grgpio_irq_unmap()
301 index = -1; in grgpio_irq_unmap()
303 lirq = &priv->lirqs[i]; in grgpio_irq_unmap()
304 if (lirq->irq == irq) { in grgpio_irq_unmap()
306 lirq->irq = 0; in grgpio_irq_unmap()
307 index = lirq->index; in grgpio_irq_unmap()
314 uirq = &priv->uirqs[lirq->index]; in grgpio_irq_unmap()
315 uirq->refcnt--; in grgpio_irq_unmap()
316 if (uirq->refcnt == 0) { in grgpio_irq_unmap()
317 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); in grgpio_irq_unmap()
318 free_irq(uirq->uirq, priv); in grgpio_irq_unmap()
323 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); in grgpio_irq_unmap()
331 /* ------------------------------------------------------------ */
335 struct device_node *np = ofdev->dev.of_node; in grgpio_probe()
346 priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL); in grgpio_probe()
348 return -ENOMEM; in grgpio_probe()
351 regs = devm_ioremap_resource(&ofdev->dev, res); in grgpio_probe()
355 gc = &priv->gc; in grgpio_probe()
356 err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA, in grgpio_probe()
360 dev_err(&ofdev->dev, "bgpio_init() failed\n"); in grgpio_probe()
364 priv->regs = regs; in grgpio_probe()
365 priv->imask = gc->read_reg(regs + GRGPIO_IMASK); in grgpio_probe()
366 priv->dev = &ofdev->dev; in grgpio_probe()
368 gc->of_node = np; in grgpio_probe()
369 gc->owner = THIS_MODULE; in grgpio_probe()
370 gc->to_irq = grgpio_to_irq; in grgpio_probe()
371 gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np); in grgpio_probe()
372 gc->base = -1; in grgpio_probe()
376 gc->ngpio = GRGPIO_MAX_NGPIO; in grgpio_probe()
377 dev_dbg(&ofdev->dev, in grgpio_probe()
378 "No or invalid nbits property: assume %d\n", gc->ngpio); in grgpio_probe()
380 gc->ngpio = prop; in grgpio_probe()
389 if (size < gc->ngpio) { in grgpio_probe()
390 dev_err(&ofdev->dev, in grgpio_probe()
392 size, gc->ngpio); in grgpio_probe()
393 return -EINVAL; in grgpio_probe()
396 priv->domain = irq_domain_add_linear(np, gc->ngpio, in grgpio_probe()
399 if (!priv->domain) { in grgpio_probe()
400 dev_err(&ofdev->dev, "Could not add irq domain\n"); in grgpio_probe()
401 return -EINVAL; in grgpio_probe()
404 for (i = 0; i < gc->ngpio; i++) { in grgpio_probe()
408 lirq = &priv->lirqs[i]; in grgpio_probe()
409 lirq->index = irqmap[i]; in grgpio_probe()
411 if (lirq->index < 0) in grgpio_probe()
414 ret = platform_get_irq(ofdev, lirq->index); in grgpio_probe()
418 * gpio line in grgpio_probe()
420 dev_err(priv->dev, in grgpio_probe()
424 priv->uirqs[lirq->index].uirq = ret; in grgpio_probe()
432 dev_err(&ofdev->dev, "Could not add gpiochip\n"); in grgpio_probe()
433 if (priv->domain) in grgpio_probe()
434 irq_domain_remove(priv->domain); in grgpio_probe()
438 dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n", in grgpio_probe()
439 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off"); in grgpio_probe()
451 spin_lock_irqsave(&priv->gc.bgpio_lock, flags); in grgpio_remove()
453 if (priv->domain) { in grgpio_remove()
455 if (priv->uirqs[i].refcnt != 0) { in grgpio_remove()
456 ret = -EBUSY; in grgpio_remove()
457 goto out; in grgpio_remove()
462 gpiochip_remove(&priv->gc); in grgpio_remove()
464 if (priv->domain) in grgpio_remove()
465 irq_domain_remove(priv->domain); in grgpio_remove()
467 out: in grgpio_remove()
468 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); in grgpio_remove()