Lines Matching +full:8 +full:- +full:ch
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
50 struct ioh_reg_comn regs[8];
58 * struct ioh_gpio_reg_data - The register store data.
78 * struct ioh_gpio - GPIO private data structure.
86 * @ch: Indicate GPIO channel
97 int ch; member
110 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_set()
111 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_set()
117 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_set()
118 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_set()
125 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr)); in ioh_gpio_get()
136 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_direction_output()
137 pm = ioread32(&chip->reg->regs[chip->ch].pm) & in ioh_gpio_direction_output()
138 ((1 << num_ports[chip->ch]) - 1); in ioh_gpio_direction_output()
140 iowrite32(pm, &chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_output()
142 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
147 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
149 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_direction_output()
160 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_direction_input()
161 pm = ioread32(&chip->reg->regs[chip->ch].pm) & in ioh_gpio_direction_input()
162 ((1 << num_ports[chip->ch]) - 1); in ioh_gpio_direction_input()
164 iowrite32(pm, &chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_input()
165 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_direction_input()
178 for (i = 0; i < 8; i ++, chip++) { in ioh_gpio_save_reg_conf()
179 chip->ioh_gpio_reg.po_reg = in ioh_gpio_save_reg_conf()
180 ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_save_reg_conf()
181 chip->ioh_gpio_reg.pm_reg = in ioh_gpio_save_reg_conf()
182 ioread32(&chip->reg->regs[chip->ch].pm); in ioh_gpio_save_reg_conf()
183 chip->ioh_gpio_reg.ien_reg = in ioh_gpio_save_reg_conf()
184 ioread32(&chip->reg->regs[chip->ch].ien); in ioh_gpio_save_reg_conf()
185 chip->ioh_gpio_reg.imask_reg = in ioh_gpio_save_reg_conf()
186 ioread32(&chip->reg->regs[chip->ch].imask); in ioh_gpio_save_reg_conf()
187 chip->ioh_gpio_reg.im0_reg = in ioh_gpio_save_reg_conf()
188 ioread32(&chip->reg->regs[chip->ch].im_0); in ioh_gpio_save_reg_conf()
189 chip->ioh_gpio_reg.im1_reg = in ioh_gpio_save_reg_conf()
190 ioread32(&chip->reg->regs[chip->ch].im_1); in ioh_gpio_save_reg_conf()
192 chip->ioh_gpio_reg.use_sel_reg = in ioh_gpio_save_reg_conf()
193 ioread32(&chip->reg->ioh_sel_reg[i]); in ioh_gpio_save_reg_conf()
204 for (i = 0; i < 8; i ++, chip++) { in ioh_gpio_restore_reg_conf()
205 iowrite32(chip->ioh_gpio_reg.po_reg, in ioh_gpio_restore_reg_conf()
206 &chip->reg->regs[chip->ch].po); in ioh_gpio_restore_reg_conf()
207 iowrite32(chip->ioh_gpio_reg.pm_reg, in ioh_gpio_restore_reg_conf()
208 &chip->reg->regs[chip->ch].pm); in ioh_gpio_restore_reg_conf()
209 iowrite32(chip->ioh_gpio_reg.ien_reg, in ioh_gpio_restore_reg_conf()
210 &chip->reg->regs[chip->ch].ien); in ioh_gpio_restore_reg_conf()
211 iowrite32(chip->ioh_gpio_reg.imask_reg, in ioh_gpio_restore_reg_conf()
212 &chip->reg->regs[chip->ch].imask); in ioh_gpio_restore_reg_conf()
213 iowrite32(chip->ioh_gpio_reg.im0_reg, in ioh_gpio_restore_reg_conf()
214 &chip->reg->regs[chip->ch].im_0); in ioh_gpio_restore_reg_conf()
215 iowrite32(chip->ioh_gpio_reg.im1_reg, in ioh_gpio_restore_reg_conf()
216 &chip->reg->regs[chip->ch].im_1); in ioh_gpio_restore_reg_conf()
218 iowrite32(chip->ioh_gpio_reg.use_sel_reg, in ioh_gpio_restore_reg_conf()
219 &chip->reg->ioh_sel_reg[i]); in ioh_gpio_restore_reg_conf()
227 return chip->irq_base + offset; in ioh_gpio_to_irq()
232 struct gpio_chip *gpio = &chip->gpio; in ioh_gpio_setup()
234 gpio->label = dev_name(chip->dev); in ioh_gpio_setup()
235 gpio->owner = THIS_MODULE; in ioh_gpio_setup()
236 gpio->direction_input = ioh_gpio_direction_input; in ioh_gpio_setup()
237 gpio->get = ioh_gpio_get; in ioh_gpio_setup()
238 gpio->direction_output = ioh_gpio_direction_output; in ioh_gpio_setup()
239 gpio->set = ioh_gpio_set; in ioh_gpio_setup()
240 gpio->dbg_show = NULL; in ioh_gpio_setup()
241 gpio->base = -1; in ioh_gpio_setup()
242 gpio->ngpio = num_port; in ioh_gpio_setup()
243 gpio->can_sleep = false; in ioh_gpio_setup()
244 gpio->to_irq = ioh_gpio_to_irq; in ioh_gpio_setup()
253 int ch; in ioh_irq_type() local
256 int irq = d->irq; in ioh_irq_type()
258 struct ioh_gpio *chip = gc->private; in ioh_irq_type()
260 ch = irq - chip->irq_base; in ioh_irq_type()
261 if (irq <= chip->irq_base + 7) { in ioh_irq_type()
262 im_reg = &chip->reg->regs[chip->ch].im_0; in ioh_irq_type()
263 im_pos = ch; in ioh_irq_type()
265 im_reg = &chip->reg->regs[chip->ch].im_1; in ioh_irq_type()
266 im_pos = ch - 8; in ioh_irq_type()
268 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n", in ioh_irq_type()
269 __func__, irq, type, ch, im_pos, type); in ioh_irq_type()
271 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_type()
292 dev_warn(chip->dev, "%s: unknown type(%dd)", in ioh_irq_type()
302 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr); in ioh_irq_type()
305 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr); in ioh_irq_type()
308 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_type()
309 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien); in ioh_irq_type()
311 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_type()
319 struct ioh_gpio *chip = gc->private; in ioh_irq_unmask()
321 iowrite32(1 << (d->irq - chip->irq_base), in ioh_irq_unmask()
322 &chip->reg->regs[chip->ch].imaskclr); in ioh_irq_unmask()
328 struct ioh_gpio *chip = gc->private; in ioh_irq_mask()
330 iowrite32(1 << (d->irq - chip->irq_base), in ioh_irq_mask()
331 &chip->reg->regs[chip->ch].imask); in ioh_irq_mask()
337 struct ioh_gpio *chip = gc->private; in ioh_irq_disable()
341 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_disable()
342 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_disable()
343 ien &= ~(1 << (d->irq - chip->irq_base)); in ioh_irq_disable()
344 iowrite32(ien, &chip->reg->regs[chip->ch].ien); in ioh_irq_disable()
345 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_disable()
351 struct ioh_gpio *chip = gc->private; in ioh_irq_enable()
355 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_enable()
356 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_enable()
357 ien |= 1 << (d->irq - chip->irq_base); in ioh_irq_enable()
358 iowrite32(ien, &chip->reg->regs[chip->ch].ien); in ioh_irq_enable()
359 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_enable()
369 for (i = 0; i < 8; i++, chip++) { in ioh_gpio_handler()
370 reg_val = ioread32(&chip->reg->regs[i].istatus); in ioh_gpio_handler()
373 dev_dbg(chip->dev, in ioh_gpio_handler()
377 &chip->reg->regs[chip->ch].iclr); in ioh_gpio_handler()
378 generic_handle_irq(chip->irq_base + j); in ioh_gpio_handler()
394 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start, in ioh_gpio_alloc_generic_chip()
395 chip->base, handle_simple_irq); in ioh_gpio_alloc_generic_chip()
397 return -ENOMEM; in ioh_gpio_alloc_generic_chip()
399 gc->private = chip; in ioh_gpio_alloc_generic_chip()
400 ct = gc->chip_types; in ioh_gpio_alloc_generic_chip()
402 ct->chip.irq_mask = ioh_irq_mask; in ioh_gpio_alloc_generic_chip()
403 ct->chip.irq_unmask = ioh_irq_unmask; in ioh_gpio_alloc_generic_chip()
404 ct->chip.irq_set_type = ioh_irq_type; in ioh_gpio_alloc_generic_chip()
405 ct->chip.irq_disable = ioh_irq_disable; in ioh_gpio_alloc_generic_chip()
406 ct->chip.irq_enable = ioh_irq_enable; in ioh_gpio_alloc_generic_chip()
408 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), in ioh_gpio_alloc_generic_chip()
427 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__); in ioh_gpio_probe()
433 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret); in ioh_gpio_probe()
439 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__); in ioh_gpio_probe()
440 ret = -ENOMEM; in ioh_gpio_probe()
444 chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL); in ioh_gpio_probe()
446 ret = -ENOMEM; in ioh_gpio_probe()
451 for (i = 0; i < 8; i++, chip++) { in ioh_gpio_probe()
452 chip->dev = &pdev->dev; in ioh_gpio_probe()
453 chip->base = base; in ioh_gpio_probe()
454 chip->reg = chip->base; in ioh_gpio_probe()
455 chip->ch = i; in ioh_gpio_probe()
456 spin_lock_init(&chip->spinlock); in ioh_gpio_probe()
458 ret = gpiochip_add_data(&chip->gpio, chip); in ioh_gpio_probe()
460 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n"); in ioh_gpio_probe()
466 for (j = 0; j < 8; j++, chip++) { in ioh_gpio_probe()
467 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE, in ioh_gpio_probe()
470 dev_warn(&pdev->dev, in ioh_gpio_probe()
475 chip->irq_base = irq_base; in ioh_gpio_probe()
484 ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler, in ioh_gpio_probe()
487 dev_err(&pdev->dev, in ioh_gpio_probe()
498 while (--i >= 0) { in ioh_gpio_probe()
499 gpiochip_remove(&chip->gpio); in ioh_gpio_probe()
515 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret); in ioh_gpio_probe()
527 for (i = 0; i < 8; i++, chip++) in ioh_gpio_remove()
528 gpiochip_remove(&chip->gpio); in ioh_gpio_remove()
531 pci_iounmap(pdev, chip->base); in ioh_gpio_remove()
544 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_suspend()
546 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_suspend()
550 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret); in ioh_gpio_suspend()
557 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret); in ioh_gpio_suspend()
573 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret); in ioh_gpio_resume()
578 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_resume()
579 iowrite32(0x01, &chip->reg->srst); in ioh_gpio_resume()
580 iowrite32(0x00, &chip->reg->srst); in ioh_gpio_resume()
582 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_resume()
608 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");