Lines Matching +full:big +full:- +full:endian +full:- +full:desc
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
55 return BIT(31 - offset); in mpc_pin2mask()
69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
71 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
82 return -EINVAL; in mpc5121_gpio_dir_out()
84 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5121_gpio_dir_out()
93 return -EINVAL; in mpc5125_gpio_dir_out()
95 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5125_gpio_dir_out()
102 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) in mpc8xxx_gpio_to_irq()
103 return irq_create_mapping(mpc8xxx_gc->irq, offset); in mpc8xxx_gpio_to_irq()
105 return -ENXIO; in mpc8xxx_gpio_to_irq()
108 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc) in mpc8xxx_gpio_irq_cascade() argument
110 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); in mpc8xxx_gpio_irq_cascade()
111 struct irq_chip *chip = irq_desc_get_chip(desc); in mpc8xxx_gpio_irq_cascade()
112 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_gpio_irq_cascade()
115 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) in mpc8xxx_gpio_irq_cascade()
116 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); in mpc8xxx_gpio_irq_cascade()
118 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, in mpc8xxx_gpio_irq_cascade()
119 32 - ffs(mask))); in mpc8xxx_gpio_irq_cascade()
120 if (chip->irq_eoi) in mpc8xxx_gpio_irq_cascade()
121 chip->irq_eoi(&desc->irq_data); in mpc8xxx_gpio_irq_cascade()
127 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_unmask()
130 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
132 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_unmask()
133 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_unmask()
136 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
142 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_mask()
145 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
147 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_mask()
148 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_mask()
151 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
157 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_ack()
159 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, in mpc8xxx_irq_ack()
166 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_set_type()
171 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
172 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
173 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
175 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
179 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
180 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
181 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
183 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
187 return -EINVAL; in mpc8xxx_irq_set_type()
196 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc512x_irq_set_type()
203 reg = mpc8xxx_gc->regs + GPIO_ICR; in mpc512x_irq_set_type()
204 shift = (15 - gpio) * 2; in mpc512x_irq_set_type()
206 reg = mpc8xxx_gc->regs + GPIO_ICR2; in mpc512x_irq_set_type()
207 shift = (15 - (gpio % 16)) * 2; in mpc512x_irq_set_type()
213 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
214 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
216 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
221 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
222 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
224 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
228 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
229 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); in mpc512x_irq_set_type()
230 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
234 return -EINVAL; in mpc512x_irq_set_type()
241 .name = "mpc8xxx-gpio",
252 irq_set_chip_data(irq, h->host_data); in mpc8xxx_gpio_irq_map()
288 { .compatible = "fsl,mpc8349-gpio", },
289 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
290 { .compatible = "fsl,mpc8610-gpio", },
291 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
292 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
293 { .compatible = "fsl,pq3-gpio", },
294 { .compatible = "fsl,qoriq-gpio", },
300 struct device_node *np = pdev->dev.of_node; in mpc8xxx_probe()
304 of_device_get_match_data(&pdev->dev); in mpc8xxx_probe()
307 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); in mpc8xxx_probe()
309 return -ENOMEM; in mpc8xxx_probe()
313 raw_spin_lock_init(&mpc8xxx_gc->lock); in mpc8xxx_probe()
315 mpc8xxx_gc->regs = of_iomap(np, 0); in mpc8xxx_probe()
316 if (!mpc8xxx_gc->regs) in mpc8xxx_probe()
317 return -ENOMEM; in mpc8xxx_probe()
319 gc = &mpc8xxx_gc->gc; in mpc8xxx_probe()
320 gc->parent = &pdev->dev; in mpc8xxx_probe()
322 if (of_property_read_bool(np, "little-endian")) { in mpc8xxx_probe()
323 ret = bgpio_init(gc, &pdev->dev, 4, in mpc8xxx_probe()
324 mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
326 mpc8xxx_gc->regs + GPIO_DIR, NULL, in mpc8xxx_probe()
330 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n"); in mpc8xxx_probe()
332 ret = bgpio_init(gc, &pdev->dev, 4, in mpc8xxx_probe()
333 mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
335 mpc8xxx_gc->regs + GPIO_DIR, NULL, in mpc8xxx_probe()
340 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n"); in mpc8xxx_probe()
343 mpc8xxx_gc->direction_output = gc->direction_output; in mpc8xxx_probe()
352 if (devtype->irq_set_type) in mpc8xxx_probe()
353 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; in mpc8xxx_probe()
355 if (devtype->gpio_dir_out) in mpc8xxx_probe()
356 gc->direction_output = devtype->gpio_dir_out; in mpc8xxx_probe()
357 if (devtype->gpio_get) in mpc8xxx_probe()
358 gc->get = devtype->gpio_get; in mpc8xxx_probe()
360 gc->to_irq = mpc8xxx_gpio_to_irq; in mpc8xxx_probe()
369 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0); in mpc8xxx_probe()
370 if (!mpc8xxx_gc->irqn) in mpc8xxx_probe()
373 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, in mpc8xxx_probe()
375 if (!mpc8xxx_gc->irq) in mpc8xxx_probe()
379 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); in mpc8xxx_probe()
380 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); in mpc8xxx_probe()
382 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, in mpc8xxx_probe()
386 iounmap(mpc8xxx_gc->regs); in mpc8xxx_probe()
394 if (mpc8xxx_gc->irq) { in mpc8xxx_remove()
395 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); in mpc8xxx_remove()
396 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_remove()
399 gpiochip_remove(&mpc8xxx_gc->gc); in mpc8xxx_remove()
400 iounmap(mpc8xxx_gc->regs); in mpc8xxx_remove()
409 .name = "gpio-mpc8xxx",