Lines Matching +full:reg +full:- +full:offset
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
31 /* the offset for the mapping of global gpio pin to irq */
65 * MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v).
74 static int msic_gpio_to_ireg(unsigned offset) in msic_gpio_to_ireg() argument
76 if (offset >= MSIC_NUM_GPIO) in msic_gpio_to_ireg()
77 return -EINVAL; in msic_gpio_to_ireg()
79 if (offset < 8) in msic_gpio_to_ireg()
80 return INTEL_MSIC_GPIO0LV0CTLI - offset; in msic_gpio_to_ireg()
81 if (offset < 16) in msic_gpio_to_ireg()
82 return INTEL_MSIC_GPIO1LV0CTLI - offset + 8; in msic_gpio_to_ireg()
83 if (offset < 20) in msic_gpio_to_ireg()
84 return INTEL_MSIC_GPIO0HV0CTLI - offset + 16; in msic_gpio_to_ireg()
86 return INTEL_MSIC_GPIO1HV0CTLI - offset + 20; in msic_gpio_to_ireg()
89 static int msic_gpio_to_oreg(unsigned offset) in msic_gpio_to_oreg() argument
91 if (offset >= MSIC_NUM_GPIO) in msic_gpio_to_oreg()
92 return -EINVAL; in msic_gpio_to_oreg()
94 if (offset < 8) in msic_gpio_to_oreg()
95 return INTEL_MSIC_GPIO0LV0CTLO - offset; in msic_gpio_to_oreg()
96 if (offset < 16) in msic_gpio_to_oreg()
97 return INTEL_MSIC_GPIO1LV0CTLO - offset + 8; in msic_gpio_to_oreg()
98 if (offset < 20) in msic_gpio_to_oreg()
99 return INTEL_MSIC_GPIO0HV0CTLO - offset + 16; in msic_gpio_to_oreg()
101 return INTEL_MSIC_GPIO1HV0CTLO - offset + 20; in msic_gpio_to_oreg()
104 static int msic_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in msic_gpio_direction_input() argument
106 int reg; in msic_gpio_direction_input() local
108 reg = msic_gpio_to_oreg(offset); in msic_gpio_direction_input()
109 if (reg < 0) in msic_gpio_direction_input()
110 return reg; in msic_gpio_direction_input()
112 return intel_msic_reg_update(reg, MSIC_GPIO_DIR_IN, MSIC_GPIO_DIR_MASK); in msic_gpio_direction_input()
116 unsigned offset, int value) in msic_gpio_direction_output() argument
118 int reg; in msic_gpio_direction_output() local
124 reg = msic_gpio_to_oreg(offset); in msic_gpio_direction_output()
125 if (reg < 0) in msic_gpio_direction_output()
126 return reg; in msic_gpio_direction_output()
128 return intel_msic_reg_update(reg, value, mask); in msic_gpio_direction_output()
131 static int msic_gpio_get(struct gpio_chip *chip, unsigned offset) in msic_gpio_get() argument
135 int reg; in msic_gpio_get() local
137 reg = msic_gpio_to_ireg(offset); in msic_gpio_get()
138 if (reg < 0) in msic_gpio_get()
139 return reg; in msic_gpio_get()
141 ret = intel_msic_reg_read(reg, &r); in msic_gpio_get()
148 static void msic_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in msic_gpio_set() argument
150 int reg; in msic_gpio_set() local
152 reg = msic_gpio_to_oreg(offset); in msic_gpio_set()
153 if (reg < 0) in msic_gpio_set()
156 intel_msic_reg_update(reg, !!value , MSIC_GPIO_DOUT_MASK); in msic_gpio_set()
160 * This is called from genirq with mg->buslock locked and
161 * irq_desc->lock held. We can not access the scu bus here, so we
167 u32 gpio = data->irq - mg->irq_base; in msic_irq_type()
169 if (gpio >= mg->chip.ngpio) in msic_irq_type()
170 return -EINVAL; in msic_irq_type()
173 mg->trig_change_mask |= (1 << gpio); in msic_irq_type()
174 mg->trig_type = type; in msic_irq_type()
179 static int msic_gpio_to_irq(struct gpio_chip *chip, unsigned offset) in msic_gpio_to_irq() argument
182 return mg->irq_base + offset; in msic_gpio_to_irq()
188 mutex_lock(&mg->buslock); in msic_bus_lock()
194 int offset; in msic_bus_sync_unlock() local
195 int reg; in msic_bus_sync_unlock() local
199 entire transaction. The irq_desc->lock is dropped before we are in msic_bus_sync_unlock()
201 if (mg->trig_change_mask) { in msic_bus_sync_unlock()
202 offset = __ffs(mg->trig_change_mask); in msic_bus_sync_unlock()
204 reg = msic_gpio_to_ireg(offset); in msic_bus_sync_unlock()
205 if (reg < 0) in msic_bus_sync_unlock()
208 if (mg->trig_type & IRQ_TYPE_EDGE_RISING) in msic_bus_sync_unlock()
210 if (mg->trig_type & IRQ_TYPE_EDGE_FALLING) in msic_bus_sync_unlock()
213 intel_msic_reg_update(reg, trig, MSIC_GPIO_INTCNT_MASK); in msic_bus_sync_unlock()
214 mg->trig_change_mask = 0; in msic_bus_sync_unlock()
217 mutex_unlock(&mg->buslock); in msic_bus_sync_unlock()
226 .name = "MSIC-GPIO",
239 struct intel_msic *msic = pdev_to_intel_msic(mg->pdev); in msic_gpio_irq_handler()
245 for (i = 0; i < (mg->chip.ngpio / BITS_PER_BYTE); i++) { in msic_gpio_irq_handler()
251 generic_handle_irq(mg->irq_base + in msic_gpio_irq_handler()
255 chip->irq_eoi(data); in msic_gpio_irq_handler()
260 struct device *dev = &pdev->dev; in platform_msic_gpio_probe()
272 if (!pdata || !pdata->gpio_base) { in platform_msic_gpio_probe()
274 return -EINVAL; in platform_msic_gpio_probe()
279 return -ENOMEM; in platform_msic_gpio_probe()
283 mg->pdev = pdev; in platform_msic_gpio_probe()
284 mg->irq = irq; in platform_msic_gpio_probe()
285 mg->irq_base = pdata->gpio_base + MSIC_GPIO_IRQ_OFFSET; in platform_msic_gpio_probe()
286 mg->chip.label = "msic_gpio"; in platform_msic_gpio_probe()
287 mg->chip.direction_input = msic_gpio_direction_input; in platform_msic_gpio_probe()
288 mg->chip.direction_output = msic_gpio_direction_output; in platform_msic_gpio_probe()
289 mg->chip.get = msic_gpio_get; in platform_msic_gpio_probe()
290 mg->chip.set = msic_gpio_set; in platform_msic_gpio_probe()
291 mg->chip.to_irq = msic_gpio_to_irq; in platform_msic_gpio_probe()
292 mg->chip.base = pdata->gpio_base; in platform_msic_gpio_probe()
293 mg->chip.ngpio = MSIC_NUM_GPIO; in platform_msic_gpio_probe()
294 mg->chip.can_sleep = true; in platform_msic_gpio_probe()
295 mg->chip.parent = dev; in platform_msic_gpio_probe()
297 mutex_init(&mg->buslock); in platform_msic_gpio_probe()
299 retval = gpiochip_add_data(&mg->chip, mg); in platform_msic_gpio_probe()
305 for (i = 0; i < mg->chip.ngpio; i++) { in platform_msic_gpio_probe()
306 irq_set_chip_data(i + mg->irq_base, mg); in platform_msic_gpio_probe()
307 irq_set_chip_and_handler(i + mg->irq_base, in platform_msic_gpio_probe()
311 irq_set_chained_handler_and_data(mg->irq, msic_gpio_irq_handler, mg); in platform_msic_gpio_probe()