Lines Matching +full:cpu +full:- +full:offset
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
22 * - the basic variant, called "orion-gpio", with the simplest
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
29 * - the armadaxp variant for Armada XP systems. This variant keeps
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
75 /* The MV78200 has per-CPU registers for edge mask and level mask */
76 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) argument
77 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) argument
80 * The Armada XP has per-CPU registers for interrupt cause, interrupt
84 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) argument
85 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) argument
86 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) argument
112 u32 offset; member
137 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_edge_cause() argument
139 int cpu; in mvebu_gpioreg_edge_cause() local
141 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_cause()
145 *map = mvchip->regs; in mvebu_gpioreg_edge_cause()
146 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; in mvebu_gpioreg_edge_cause()
149 cpu = smp_processor_id(); in mvebu_gpioreg_edge_cause()
150 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_cause()
151 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); in mvebu_gpioreg_edge_cause()
162 unsigned int offset; in mvebu_gpio_read_edge_cause() local
165 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_read_edge_cause()
166 regmap_read(map, offset, &val); in mvebu_gpio_read_edge_cause()
175 unsigned int offset; in mvebu_gpio_write_edge_cause() local
177 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_write_edge_cause()
178 regmap_write(map, offset, val); in mvebu_gpio_write_edge_cause()
183 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_edge_mask() argument
185 int cpu; in mvebu_gpioreg_edge_mask() local
187 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_mask()
190 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
191 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; in mvebu_gpioreg_edge_mask()
194 cpu = smp_processor_id(); in mvebu_gpioreg_edge_mask()
195 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
196 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); in mvebu_gpioreg_edge_mask()
199 cpu = smp_processor_id(); in mvebu_gpioreg_edge_mask()
200 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_mask()
201 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); in mvebu_gpioreg_edge_mask()
212 unsigned int offset; in mvebu_gpio_read_edge_mask() local
215 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_read_edge_mask()
216 regmap_read(map, offset, &val); in mvebu_gpio_read_edge_mask()
225 unsigned int offset; in mvebu_gpio_write_edge_mask() local
227 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_write_edge_mask()
228 regmap_write(map, offset, val); in mvebu_gpio_write_edge_mask()
233 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_level_mask() argument
235 int cpu; in mvebu_gpioreg_level_mask() local
237 switch (mvchip->soc_variant) { in mvebu_gpioreg_level_mask()
240 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
241 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; in mvebu_gpioreg_level_mask()
244 cpu = smp_processor_id(); in mvebu_gpioreg_level_mask()
245 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
246 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); in mvebu_gpioreg_level_mask()
249 cpu = smp_processor_id(); in mvebu_gpioreg_level_mask()
250 *map = mvchip->percpu_regs; in mvebu_gpioreg_level_mask()
251 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); in mvebu_gpioreg_level_mask()
262 unsigned int offset; in mvebu_gpio_read_level_mask() local
265 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_read_level_mask()
266 regmap_read(map, offset, &val); in mvebu_gpio_read_level_mask()
275 unsigned int offset; in mvebu_gpio_write_level_mask() local
277 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_write_level_mask()
278 regmap_write(map, offset, val); in mvebu_gpio_write_level_mask()
287 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF; in mvebu_pwmreg_blink_on_duration()
292 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF; in mvebu_pwmreg_blink_off_duration()
302 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_set()
311 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get()
316 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, in mvebu_gpio_get()
318 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_get()
322 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); in mvebu_gpio_get()
333 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_blink()
346 ret = pinctrl_gpio_direction_input(chip->base + pin); in mvebu_gpio_direction_input()
350 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_input()
366 ret = pinctrl_gpio_direction_output(chip->base + pin); in mvebu_gpio_direction_output()
373 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_output()
383 return irq_create_mapping(mvchip->domain, pin); in mvebu_gpio_to_irq()
392 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_ack()
393 u32 mask = d->mask; in mvebu_gpio_irq_ack()
403 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_mask()
405 u32 mask = d->mask; in mvebu_gpio_edge_irq_mask()
408 ct->mask_cache_priv &= ~mask; in mvebu_gpio_edge_irq_mask()
409 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_mask()
416 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_unmask()
418 u32 mask = d->mask; in mvebu_gpio_edge_irq_unmask()
421 ct->mask_cache_priv |= mask; in mvebu_gpio_edge_irq_unmask()
422 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_unmask()
429 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_mask()
431 u32 mask = d->mask; in mvebu_gpio_level_irq_mask()
434 ct->mask_cache_priv &= ~mask; in mvebu_gpio_level_irq_mask()
435 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_mask()
442 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_unmask()
444 u32 mask = d->mask; in mvebu_gpio_level_irq_unmask()
447 ct->mask_cache_priv |= mask; in mvebu_gpio_level_irq_unmask()
448 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_unmask()
462 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
471 * data-in /--------| |-----| |----\
472 * -----| |----- ---- to main cause reg
473 * X \----------------| |----/
482 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_set_type()
486 pin = d->hwirq; in mvebu_gpio_irq_set_type()
488 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_irq_set_type()
490 return -EINVAL; in mvebu_gpio_irq_set_type()
494 return -EINVAL; in mvebu_gpio_irq_set_type()
497 if (!(ct->type & type)) in mvebu_gpio_irq_set_type()
499 return -EINVAL; in mvebu_gpio_irq_set_type()
507 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
508 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
513 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
514 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
520 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
521 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_irq_set_type()
522 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
523 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_set_type()
533 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
534 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
554 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_handler()
561 for (i = 0; i < mvchip->chip.ngpio; i++) { in mvebu_gpio_irq_handler()
564 irq = irq_find_mapping(mvchip->domain, i); in mvebu_gpio_irq_handler()
574 regmap_read(mvchip->regs, in mvebu_gpio_irq_handler()
575 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
578 regmap_write(mvchip->regs, in mvebu_gpio_irq_handler()
579 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
600 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_request()
605 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_request()
607 if (mvpwm->gpiod) { in mvebu_pwm_request()
608 ret = -EBUSY; in mvebu_pwm_request()
610 desc = gpiochip_request_own_desc(&mvchip->chip, in mvebu_pwm_request()
611 pwm->hwpwm, "mvebu-pwm"); in mvebu_pwm_request()
623 mvpwm->gpiod = desc; in mvebu_pwm_request()
626 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_request()
635 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_free()
636 gpiochip_free_own_desc(mvpwm->gpiod); in mvebu_pwm_free()
637 mvpwm->gpiod = NULL; in mvebu_pwm_free()
638 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_free()
646 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_get_state()
651 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_get_state()
656 do_div(val, mvpwm->clk_rate); in mvebu_pwm_get_state()
658 state->duty_cycle = UINT_MAX; in mvebu_pwm_get_state()
660 state->duty_cycle = val; in mvebu_pwm_get_state()
662 state->duty_cycle = 1; in mvebu_pwm_get_state()
667 do_div(val, mvpwm->clk_rate); in mvebu_pwm_get_state()
668 if (val < state->duty_cycle) { in mvebu_pwm_get_state()
669 state->period = 1; in mvebu_pwm_get_state()
671 val -= state->duty_cycle; in mvebu_pwm_get_state()
673 state->period = UINT_MAX; in mvebu_pwm_get_state()
675 state->period = val; in mvebu_pwm_get_state()
677 state->period = 1; in mvebu_pwm_get_state()
680 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); in mvebu_pwm_get_state()
682 state->enabled = true; in mvebu_pwm_get_state()
684 state->enabled = false; in mvebu_pwm_get_state()
686 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_get_state()
693 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_apply()
698 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; in mvebu_pwm_apply()
701 return -EINVAL; in mvebu_pwm_apply()
707 val = (unsigned long long) mvpwm->clk_rate * in mvebu_pwm_apply()
708 (state->period - state->duty_cycle); in mvebu_pwm_apply()
711 return -EINVAL; in mvebu_pwm_apply()
717 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_apply()
721 if (state->enabled) in mvebu_pwm_apply()
722 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); in mvebu_pwm_apply()
724 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); in mvebu_pwm_apply()
726 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_apply()
741 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_suspend()
743 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_suspend()
744 &mvpwm->blink_select); in mvebu_pwm_suspend()
745 mvpwm->blink_on_duration = in mvebu_pwm_suspend()
747 mvpwm->blink_off_duration = in mvebu_pwm_suspend()
753 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_resume()
755 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_resume()
756 mvpwm->blink_select); in mvebu_pwm_resume()
757 writel_relaxed(mvpwm->blink_on_duration, in mvebu_pwm_resume()
759 writel_relaxed(mvpwm->blink_off_duration, in mvebu_pwm_resume()
767 struct device *dev = &pdev->dev; in mvebu_pwm_probe()
772 if (!of_device_is_compatible(mvchip->chip.of_node, in mvebu_pwm_probe()
773 "marvell,armada-370-gpio")) in mvebu_pwm_probe()
786 if (IS_ERR(mvchip->clk)) in mvebu_pwm_probe()
787 return PTR_ERR(mvchip->clk); in mvebu_pwm_probe()
798 return -EINVAL; in mvebu_pwm_probe()
799 regmap_write(mvchip->regs, in mvebu_pwm_probe()
800 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); in mvebu_pwm_probe()
804 return -ENOMEM; in mvebu_pwm_probe()
805 mvchip->mvpwm = mvpwm; in mvebu_pwm_probe()
806 mvpwm->mvchip = mvchip; in mvebu_pwm_probe()
808 mvpwm->membase = devm_ioremap_resource(dev, res); in mvebu_pwm_probe()
809 if (IS_ERR(mvpwm->membase)) in mvebu_pwm_probe()
810 return PTR_ERR(mvpwm->membase); in mvebu_pwm_probe()
812 mvpwm->clk_rate = clk_get_rate(mvchip->clk); in mvebu_pwm_probe()
813 if (!mvpwm->clk_rate) { in mvebu_pwm_probe()
815 return -EINVAL; in mvebu_pwm_probe()
818 mvpwm->chip.dev = dev; in mvebu_pwm_probe()
819 mvpwm->chip.ops = &mvebu_pwm_ops; in mvebu_pwm_probe()
820 mvpwm->chip.npwm = mvchip->chip.ngpio; in mvebu_pwm_probe()
823 * mvpwm->chip.base to a fixed point like mvchip->chip.base. in mvebu_pwm_probe()
827 mvpwm->chip.base = -1; in mvebu_pwm_probe()
829 spin_lock_init(&mvpwm->lock); in mvebu_pwm_probe()
831 return pwmchip_add(&mvpwm->chip); in mvebu_pwm_probe()
843 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); in mvebu_gpio_dbg_show()
844 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); in mvebu_gpio_dbg_show()
845 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); in mvebu_gpio_dbg_show()
846 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_dbg_show()
847 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_dbg_show()
852 for (i = 0; i < chip->ngpio; i++) { in mvebu_gpio_dbg_show()
864 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); in mvebu_gpio_dbg_show()
873 seq_printf(s, " in %s (act %s) - IRQ", in mvebu_gpio_dbg_show()
893 .compatible = "marvell,orion-gpio",
897 .compatible = "marvell,mv78200-gpio",
901 .compatible = "marvell,armadaxp-gpio",
905 .compatible = "marvell,armada-370-gpio",
909 .compatible = "marvell,armada-8k-gpio",
922 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_suspend()
923 &mvchip->out_reg); in mvebu_gpio_suspend()
924 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_suspend()
925 &mvchip->io_conf_reg); in mvebu_gpio_suspend()
926 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_suspend()
927 &mvchip->blink_en_reg); in mvebu_gpio_suspend()
928 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_suspend()
929 &mvchip->in_pol_reg); in mvebu_gpio_suspend()
931 switch (mvchip->soc_variant) { in mvebu_gpio_suspend()
934 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
935 &mvchip->edge_mask_regs[0]); in mvebu_gpio_suspend()
936 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
937 &mvchip->level_mask_regs[0]); in mvebu_gpio_suspend()
941 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
943 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
944 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
946 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
951 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
953 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
954 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
956 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
974 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_resume()
975 mvchip->out_reg); in mvebu_gpio_resume()
976 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_resume()
977 mvchip->io_conf_reg); in mvebu_gpio_resume()
978 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_resume()
979 mvchip->blink_en_reg); in mvebu_gpio_resume()
980 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_resume()
981 mvchip->in_pol_reg); in mvebu_gpio_resume()
983 switch (mvchip->soc_variant) { in mvebu_gpio_resume()
986 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
987 mvchip->edge_mask_regs[0]); in mvebu_gpio_resume()
988 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
989 mvchip->level_mask_regs[0]); in mvebu_gpio_resume()
993 regmap_write(mvchip->regs, in mvebu_gpio_resume()
995 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
996 regmap_write(mvchip->regs, in mvebu_gpio_resume()
998 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1003 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1005 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1006 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1008 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1035 base = devm_ioremap_resource(&pdev->dev, res); in mvebu_gpio_probe_raw()
1039 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1041 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_raw()
1042 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_raw()
1046 * registers, so no offset is needed. in mvebu_gpio_probe_raw()
1048 mvchip->offset = 0; in mvebu_gpio_probe_raw()
1052 * per-CPU registers in mvebu_gpio_probe_raw()
1054 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { in mvebu_gpio_probe_raw()
1056 base = devm_ioremap_resource(&pdev->dev, res); in mvebu_gpio_probe_raw()
1060 mvchip->percpu_regs = in mvebu_gpio_probe_raw()
1061 devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1063 if (IS_ERR(mvchip->percpu_regs)) in mvebu_gpio_probe_raw()
1064 return PTR_ERR(mvchip->percpu_regs); in mvebu_gpio_probe_raw()
1073 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); in mvebu_gpio_probe_syscon()
1074 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_syscon()
1075 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_syscon()
1077 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) in mvebu_gpio_probe_syscon()
1078 return -EINVAL; in mvebu_gpio_probe_syscon()
1087 struct device_node *np = pdev->dev.of_node; in mvebu_gpio_probe()
1093 int i, cpu, id; in mvebu_gpio_probe() local
1096 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); in mvebu_gpio_probe()
1098 soc_variant = (unsigned long) match->data; in mvebu_gpio_probe()
1105 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), in mvebu_gpio_probe()
1108 return -ENOMEM; in mvebu_gpio_probe()
1112 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { in mvebu_gpio_probe()
1113 dev_err(&pdev->dev, "Missing ngpios OF property\n"); in mvebu_gpio_probe()
1114 return -ENODEV; in mvebu_gpio_probe()
1117 id = of_alias_get_id(pdev->dev.of_node, "gpio"); in mvebu_gpio_probe()
1119 dev_err(&pdev->dev, "Couldn't get OF id\n"); in mvebu_gpio_probe()
1123 mvchip->clk = devm_clk_get(&pdev->dev, NULL); in mvebu_gpio_probe()
1125 if (!IS_ERR(mvchip->clk)) in mvebu_gpio_probe()
1126 clk_prepare_enable(mvchip->clk); in mvebu_gpio_probe()
1128 mvchip->soc_variant = soc_variant; in mvebu_gpio_probe()
1129 mvchip->chip.label = dev_name(&pdev->dev); in mvebu_gpio_probe()
1130 mvchip->chip.parent = &pdev->dev; in mvebu_gpio_probe()
1131 mvchip->chip.request = gpiochip_generic_request; in mvebu_gpio_probe()
1132 mvchip->chip.free = gpiochip_generic_free; in mvebu_gpio_probe()
1133 mvchip->chip.direction_input = mvebu_gpio_direction_input; in mvebu_gpio_probe()
1134 mvchip->chip.get = mvebu_gpio_get; in mvebu_gpio_probe()
1135 mvchip->chip.direction_output = mvebu_gpio_direction_output; in mvebu_gpio_probe()
1136 mvchip->chip.set = mvebu_gpio_set; in mvebu_gpio_probe()
1138 mvchip->chip.to_irq = mvebu_gpio_to_irq; in mvebu_gpio_probe()
1139 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; in mvebu_gpio_probe()
1140 mvchip->chip.ngpio = ngpios; in mvebu_gpio_probe()
1141 mvchip->chip.can_sleep = false; in mvebu_gpio_probe()
1142 mvchip->chip.of_node = np; in mvebu_gpio_probe()
1143 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; in mvebu_gpio_probe()
1159 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1160 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1161 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1162 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1163 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1164 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1167 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1168 for (cpu = 0; cpu < 2; cpu++) { in mvebu_gpio_probe()
1169 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1170 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); in mvebu_gpio_probe()
1171 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1172 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); in mvebu_gpio_probe()
1176 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1177 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); in mvebu_gpio_probe()
1178 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); in mvebu_gpio_probe()
1179 for (cpu = 0; cpu < 4; cpu++) { in mvebu_gpio_probe()
1180 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1181 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); in mvebu_gpio_probe()
1182 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1183 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); in mvebu_gpio_probe()
1184 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1185 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); in mvebu_gpio_probe()
1192 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); in mvebu_gpio_probe()
1198 mvchip->domain = in mvebu_gpio_probe()
1200 if (!mvchip->domain) { in mvebu_gpio_probe()
1201 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", in mvebu_gpio_probe()
1202 mvchip->chip.label); in mvebu_gpio_probe()
1203 return -ENODEV; in mvebu_gpio_probe()
1207 mvchip->domain, ngpios, 2, np->name, handle_level_irq, in mvebu_gpio_probe()
1210 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", in mvebu_gpio_probe()
1211 mvchip->chip.label); in mvebu_gpio_probe()
1219 gc = irq_get_domain_generic_chip(mvchip->domain, 0); in mvebu_gpio_probe()
1220 gc->private = mvchip; in mvebu_gpio_probe()
1221 ct = &gc->chip_types[0]; in mvebu_gpio_probe()
1222 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; in mvebu_gpio_probe()
1223 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; in mvebu_gpio_probe()
1224 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; in mvebu_gpio_probe()
1225 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1226 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1228 ct = &gc->chip_types[1]; in mvebu_gpio_probe()
1229 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; in mvebu_gpio_probe()
1230 ct->chip.irq_ack = mvebu_gpio_irq_ack; in mvebu_gpio_probe()
1231 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; in mvebu_gpio_probe()
1232 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; in mvebu_gpio_probe()
1233 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1234 ct->handler = handle_edge_irq; in mvebu_gpio_probe()
1235 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1258 irq_domain_remove(mvchip->domain); in mvebu_gpio_probe()
1265 .name = "mvebu-gpio",