Lines Matching full:bank
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 void (*set_dataout_multiple)(struct gpio_bank *bank,
89 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
100 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
103 void __iomem *reg = bank->base; in omap_set_gpio_direction()
106 reg += bank->regs->direction; in omap_set_gpio_direction()
113 bank->context.oe = l; in omap_set_gpio_direction()
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
129 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
136 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_mask() argument
139 void __iomem *reg = bank->base + bank->regs->dataout; in omap_set_gpio_dataout_mask()
149 bank->context.dataout = l; in omap_set_gpio_dataout_mask()
152 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) in omap_get_gpio_datain() argument
154 void __iomem *reg = bank->base + bank->regs->datain; in omap_get_gpio_datain()
159 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) in omap_get_gpio_dataout() argument
161 void __iomem *reg = bank->base + bank->regs->dataout; in omap_get_gpio_dataout()
167 static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank, in omap_set_gpio_dataout_reg_multiple() argument
171 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg_multiple()
175 writel_relaxed(l, reg + bank->regs->set_dataout); in omap_set_gpio_dataout_reg_multiple()
176 bank->context.dataout |= l; in omap_set_gpio_dataout_reg_multiple()
179 writel_relaxed(l, reg + bank->regs->clr_dataout); in omap_set_gpio_dataout_reg_multiple()
180 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg_multiple()
184 static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank, in omap_set_gpio_dataout_mask_multiple() argument
188 void __iomem *reg = bank->base + bank->regs->dataout; in omap_set_gpio_dataout_mask_multiple()
192 bank->context.dataout = l; in omap_set_gpio_dataout_mask_multiple()
195 static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank, in omap_get_gpio_datain_multiple() argument
198 void __iomem *reg = bank->base + bank->regs->datain; in omap_get_gpio_datain_multiple()
203 static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank, in omap_get_gpio_dataout_multiple() argument
206 void __iomem *reg = bank->base + bank->regs->dataout; in omap_get_gpio_dataout_multiple()
223 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) in omap_gpio_dbck_enable() argument
225 if (bank->dbck_enable_mask && !bank->dbck_enabled) { in omap_gpio_dbck_enable()
226 clk_enable(bank->dbck); in omap_gpio_dbck_enable()
227 bank->dbck_enabled = true; in omap_gpio_dbck_enable()
229 writel_relaxed(bank->dbck_enable_mask, in omap_gpio_dbck_enable()
230 bank->base + bank->regs->debounce_en); in omap_gpio_dbck_enable()
234 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) in omap_gpio_dbck_disable() argument
236 if (bank->dbck_enable_mask && bank->dbck_enabled) { in omap_gpio_dbck_disable()
242 writel_relaxed(0, bank->base + bank->regs->debounce_en); in omap_gpio_dbck_disable()
244 clk_disable(bank->dbck); in omap_gpio_dbck_disable()
245 bank->dbck_enabled = false; in omap_gpio_dbck_disable()
251 * @bank: the gpio bank we're acting upon
252 * @offset: the gpio number on this @bank
261 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, in omap2_set_gpio_debounce() argument
269 if (!bank->dbck_flag) in omap2_set_gpio_debounce()
280 clk_enable(bank->dbck); in omap2_set_gpio_debounce()
281 reg = bank->base + bank->regs->debounce; in omap2_set_gpio_debounce()
284 reg = bank->base + bank->regs->debounce_en; in omap2_set_gpio_debounce()
291 bank->dbck_enable_mask = val; in omap2_set_gpio_debounce()
294 clk_disable(bank->dbck); in omap2_set_gpio_debounce()
303 omap_gpio_dbck_enable(bank); in omap2_set_gpio_debounce()
304 if (bank->dbck_enable_mask) { in omap2_set_gpio_debounce()
305 bank->context.debounce = debounce; in omap2_set_gpio_debounce()
306 bank->context.debounce_en = val; in omap2_set_gpio_debounce()
314 * @bank: the gpio bank we're acting upon
315 * @offset: the gpio number on this @bank
318 * this is the only gpio in this bank using debounce, then clear the debounce
320 * if this is the only gpio in the bank using debounce.
322 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) in omap_clear_gpio_debounce() argument
326 if (!bank->dbck_flag) in omap_clear_gpio_debounce()
329 if (!(bank->dbck_enable_mask & gpio_bit)) in omap_clear_gpio_debounce()
332 bank->dbck_enable_mask &= ~gpio_bit; in omap_clear_gpio_debounce()
333 bank->context.debounce_en &= ~gpio_bit; in omap_clear_gpio_debounce()
334 writel_relaxed(bank->context.debounce_en, in omap_clear_gpio_debounce()
335 bank->base + bank->regs->debounce_en); in omap_clear_gpio_debounce()
337 if (!bank->dbck_enable_mask) { in omap_clear_gpio_debounce()
338 bank->context.debounce = 0; in omap_clear_gpio_debounce()
339 writel_relaxed(bank->context.debounce, bank->base + in omap_clear_gpio_debounce()
340 bank->regs->debounce); in omap_clear_gpio_debounce()
341 clk_disable(bank->dbck); in omap_clear_gpio_debounce()
342 bank->dbck_enabled = false; in omap_clear_gpio_debounce()
347 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
349 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
352 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) in omap_gpio_is_off_wakeup_capable() argument
354 u32 no_wake = bank->non_wakeup_gpios; in omap_gpio_is_off_wakeup_capable()
362 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, in omap_set_gpio_trigger() argument
365 void __iomem *base = bank->base; in omap_set_gpio_trigger()
368 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, in omap_set_gpio_trigger()
370 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, in omap_set_gpio_trigger()
372 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, in omap_set_gpio_trigger()
374 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, in omap_set_gpio_trigger()
377 bank->context.leveldetect0 = in omap_set_gpio_trigger()
378 readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_set_gpio_trigger()
379 bank->context.leveldetect1 = in omap_set_gpio_trigger()
380 readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_set_gpio_trigger()
381 bank->context.risingdetect = in omap_set_gpio_trigger()
382 readl_relaxed(bank->base + bank->regs->risingdetect); in omap_set_gpio_trigger()
383 bank->context.fallingdetect = in omap_set_gpio_trigger()
384 readl_relaxed(bank->base + bank->regs->fallingdetect); in omap_set_gpio_trigger()
386 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { in omap_set_gpio_trigger()
387 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); in omap_set_gpio_trigger()
388 bank->context.wake_en = in omap_set_gpio_trigger()
389 readl_relaxed(bank->base + bank->regs->wkup_en); in omap_set_gpio_trigger()
393 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { in omap_set_gpio_trigger()
401 bank->enabled_non_wakeup_gpios |= gpio_bit; in omap_set_gpio_trigger()
403 bank->enabled_non_wakeup_gpios &= ~gpio_bit; in omap_set_gpio_trigger()
406 bank->level_mask = in omap_set_gpio_trigger()
407 readl_relaxed(bank->base + bank->regs->leveldetect0) | in omap_set_gpio_trigger()
408 readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_set_gpio_trigger()
416 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) in omap_toggle_gpio_edge_triggering() argument
418 void __iomem *reg = bank->base; in omap_toggle_gpio_edge_triggering()
421 if (!bank->regs->irqctrl) in omap_toggle_gpio_edge_triggering()
424 reg += bank->regs->irqctrl; in omap_toggle_gpio_edge_triggering()
435 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} in omap_toggle_gpio_edge_triggering() argument
438 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, in omap_set_gpio_triggering() argument
441 void __iomem *reg = bank->base; in omap_set_gpio_triggering()
442 void __iomem *base = bank->base; in omap_set_gpio_triggering()
445 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { in omap_set_gpio_triggering()
446 omap_set_gpio_trigger(bank, gpio, trigger); in omap_set_gpio_triggering()
447 } else if (bank->regs->irqctrl) { in omap_set_gpio_triggering()
448 reg += bank->regs->irqctrl; in omap_set_gpio_triggering()
452 bank->toggle_mask |= BIT(gpio); in omap_set_gpio_triggering()
461 } else if (bank->regs->edgectrl1) { in omap_set_gpio_triggering()
463 reg += bank->regs->edgectrl2; in omap_set_gpio_triggering()
465 reg += bank->regs->edgectrl1; in omap_set_gpio_triggering()
476 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); in omap_set_gpio_triggering()
477 bank->context.wake_en = in omap_set_gpio_triggering()
478 readl_relaxed(bank->base + bank->regs->wkup_en); in omap_set_gpio_triggering()
484 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) in omap_enable_gpio_module() argument
486 if (bank->regs->pinctrl) { in omap_enable_gpio_module()
487 void __iomem *reg = bank->base + bank->regs->pinctrl; in omap_enable_gpio_module()
493 if (bank->regs->ctrl && !BANK_USED(bank)) { in omap_enable_gpio_module()
494 void __iomem *reg = bank->base + bank->regs->ctrl; in omap_enable_gpio_module()
501 bank->context.ctrl = ctrl; in omap_enable_gpio_module()
505 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) in omap_disable_gpio_module() argument
507 void __iomem *base = bank->base; in omap_disable_gpio_module()
509 if (bank->regs->wkup_en && in omap_disable_gpio_module()
510 !LINE_USED(bank->mod_usage, offset) && in omap_disable_gpio_module()
511 !LINE_USED(bank->irq_usage, offset)) { in omap_disable_gpio_module()
513 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); in omap_disable_gpio_module()
514 bank->context.wake_en = in omap_disable_gpio_module()
515 readl_relaxed(bank->base + bank->regs->wkup_en); in omap_disable_gpio_module()
518 if (bank->regs->ctrl && !BANK_USED(bank)) { in omap_disable_gpio_module()
519 void __iomem *reg = bank->base + bank->regs->ctrl; in omap_disable_gpio_module()
526 bank->context.ctrl = ctrl; in omap_disable_gpio_module()
530 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) in omap_gpio_is_input() argument
532 void __iomem *reg = bank->base + bank->regs->direction; in omap_gpio_is_input()
537 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) in omap_gpio_init_irq() argument
539 if (!LINE_USED(bank->mod_usage, offset)) { in omap_gpio_init_irq()
540 omap_enable_gpio_module(bank, offset); in omap_gpio_init_irq()
541 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_init_irq()
543 bank->irq_usage |= BIT(offset); in omap_gpio_init_irq()
548 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_irq_type() local
556 if (!bank->regs->leveldetect0 && in omap_gpio_irq_type()
560 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_type()
561 retval = omap_set_gpio_triggering(bank, offset, type); in omap_gpio_irq_type()
563 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
566 omap_gpio_init_irq(bank, offset); in omap_gpio_irq_type()
567 if (!omap_gpio_is_input(bank, offset)) { in omap_gpio_irq_type()
568 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
572 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
591 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) in omap_clear_gpio_irqbank() argument
593 void __iomem *reg = bank->base; in omap_clear_gpio_irqbank()
595 reg += bank->regs->irqstatus; in omap_clear_gpio_irqbank()
599 if (bank->regs->irqstatus2) { in omap_clear_gpio_irqbank()
600 reg = bank->base + bank->regs->irqstatus2; in omap_clear_gpio_irqbank()
608 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, in omap_clear_gpio_irqstatus() argument
611 omap_clear_gpio_irqbank(bank, BIT(offset)); in omap_clear_gpio_irqstatus()
614 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) in omap_get_gpio_irqbank_mask() argument
616 void __iomem *reg = bank->base; in omap_get_gpio_irqbank_mask()
618 u32 mask = (BIT(bank->width)) - 1; in omap_get_gpio_irqbank_mask()
620 reg += bank->regs->irqenable; in omap_get_gpio_irqbank_mask()
622 if (bank->regs->irqenable_inv) in omap_get_gpio_irqbank_mask()
628 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) in omap_enable_gpio_irqbank() argument
630 void __iomem *reg = bank->base; in omap_enable_gpio_irqbank()
633 if (bank->regs->set_irqenable) { in omap_enable_gpio_irqbank()
634 reg += bank->regs->set_irqenable; in omap_enable_gpio_irqbank()
636 bank->context.irqenable1 |= gpio_mask; in omap_enable_gpio_irqbank()
638 reg += bank->regs->irqenable; in omap_enable_gpio_irqbank()
640 if (bank->regs->irqenable_inv) in omap_enable_gpio_irqbank()
644 bank->context.irqenable1 = l; in omap_enable_gpio_irqbank()
650 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) in omap_disable_gpio_irqbank() argument
652 void __iomem *reg = bank->base; in omap_disable_gpio_irqbank()
655 if (bank->regs->clr_irqenable) { in omap_disable_gpio_irqbank()
656 reg += bank->regs->clr_irqenable; in omap_disable_gpio_irqbank()
658 bank->context.irqenable1 &= ~gpio_mask; in omap_disable_gpio_irqbank()
660 reg += bank->regs->irqenable; in omap_disable_gpio_irqbank()
662 if (bank->regs->irqenable_inv) in omap_disable_gpio_irqbank()
666 bank->context.irqenable1 = l; in omap_disable_gpio_irqbank()
672 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, in omap_set_gpio_irqenable() argument
676 omap_enable_gpio_irqbank(bank, BIT(offset)); in omap_set_gpio_irqenable()
678 omap_disable_gpio_irqbank(bank, BIT(offset)); in omap_set_gpio_irqenable()
684 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_wake_enable() local
686 return irq_set_irq_wake(bank->irq, enable); in omap_gpio_wake_enable()
691 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_request() local
695 * If this is the first gpio_request for the bank, in omap_gpio_request()
696 * enable the bank module. in omap_gpio_request()
698 if (!BANK_USED(bank)) in omap_gpio_request()
701 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_request()
702 omap_enable_gpio_module(bank, offset); in omap_gpio_request()
703 bank->mod_usage |= BIT(offset); in omap_gpio_request()
704 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_request()
711 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_free() local
714 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_free()
715 bank->mod_usage &= ~(BIT(offset)); in omap_gpio_free()
716 if (!LINE_USED(bank->irq_usage, offset)) { in omap_gpio_free()
717 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_free()
718 omap_clear_gpio_debounce(bank, offset); in omap_gpio_free()
720 omap_disable_gpio_module(bank, offset); in omap_gpio_free()
721 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_free()
724 * If this is the last gpio to be freed in the bank, in omap_gpio_free()
725 * disable the bank module. in omap_gpio_free()
727 if (!BANK_USED(bank)) in omap_gpio_free()
732 * We need to unmask the GPIO bank interrupt as soon as possible to
733 * avoid missing GPIO interrupts for other lines in the bank.
735 * in the bank to avoid missing nested interrupts for a GPIO line.
736 * If we wait to unmask individual GPIO lines in the bank after the
745 struct gpio_bank *bank = gpiobank; in omap_gpio_irq_handler() local
749 isr_reg = bank->base + bank->regs->irqstatus; in omap_gpio_irq_handler()
753 pm_runtime_get_sync(bank->chip.parent); in omap_gpio_irq_handler()
756 raw_spin_lock_irqsave(&bank->lock, lock_flags); in omap_gpio_irq_handler()
758 enabled = omap_get_gpio_irqbank_mask(bank); in omap_gpio_irq_handler()
761 if (bank->level_mask) in omap_gpio_irq_handler()
762 level_mask = bank->level_mask & enabled; in omap_gpio_irq_handler()
770 omap_clear_gpio_irqbank(bank, isr & ~level_mask); in omap_gpio_irq_handler()
772 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); in omap_gpio_irq_handler()
781 raw_spin_lock_irqsave(&bank->lock, lock_flags); in omap_gpio_irq_handler()
787 * This will be indicated in the bank toggle_mask. in omap_gpio_irq_handler()
789 if (bank->toggle_mask & (BIT(bit))) in omap_gpio_irq_handler()
790 omap_toggle_gpio_edge_triggering(bank, bit); in omap_gpio_irq_handler()
792 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); in omap_gpio_irq_handler()
794 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); in omap_gpio_irq_handler()
796 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, in omap_gpio_irq_handler()
799 raw_spin_unlock_irqrestore(&bank->wa_lock, in omap_gpio_irq_handler()
804 pm_runtime_put(bank->chip.parent); in omap_gpio_irq_handler()
810 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_irq_startup() local
814 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_startup()
816 if (!LINE_USED(bank->mod_usage, offset)) in omap_gpio_irq_startup()
817 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_irq_startup()
818 else if (!omap_gpio_is_input(bank, offset)) in omap_gpio_irq_startup()
820 omap_enable_gpio_module(bank, offset); in omap_gpio_irq_startup()
821 bank->irq_usage |= BIT(offset); in omap_gpio_irq_startup()
823 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_startup()
828 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_startup()
834 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_irq_shutdown() local
838 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_shutdown()
839 bank->irq_usage &= ~(BIT(offset)); in omap_gpio_irq_shutdown()
840 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); in omap_gpio_irq_shutdown()
841 omap_clear_gpio_irqstatus(bank, offset); in omap_gpio_irq_shutdown()
842 omap_set_gpio_irqenable(bank, offset, 0); in omap_gpio_irq_shutdown()
843 if (!LINE_USED(bank->mod_usage, offset)) in omap_gpio_irq_shutdown()
844 omap_clear_gpio_debounce(bank, offset); in omap_gpio_irq_shutdown()
845 omap_disable_gpio_module(bank, offset); in omap_gpio_irq_shutdown()
846 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_shutdown()
851 struct gpio_bank *bank = omap_irq_data_get_bank(data); in omap_gpio_irq_bus_lock() local
853 if (!BANK_USED(bank)) in omap_gpio_irq_bus_lock()
854 pm_runtime_get_sync(bank->chip.parent); in omap_gpio_irq_bus_lock()
859 struct gpio_bank *bank = omap_irq_data_get_bank(data); in gpio_irq_bus_sync_unlock() local
862 * If this is the last IRQ to be freed in the bank, in gpio_irq_bus_sync_unlock()
863 * disable the bank module. in gpio_irq_bus_sync_unlock()
865 if (!BANK_USED(bank)) in gpio_irq_bus_sync_unlock()
866 pm_runtime_put(bank->chip.parent); in gpio_irq_bus_sync_unlock()
871 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_ack_irq() local
874 omap_clear_gpio_irqstatus(bank, offset); in omap_gpio_ack_irq()
879 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_mask_irq() local
883 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_mask_irq()
884 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); in omap_gpio_mask_irq()
885 omap_set_gpio_irqenable(bank, offset, 0); in omap_gpio_mask_irq()
886 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_mask_irq()
891 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_unmask_irq() local
896 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_unmask_irq()
897 omap_set_gpio_irqenable(bank, offset, 1); in omap_gpio_unmask_irq()
904 if (bank->regs->leveldetect0 && bank->regs->wkup_en && in omap_gpio_unmask_irq()
906 omap_clear_gpio_irqstatus(bank, offset); in omap_gpio_unmask_irq()
909 omap_set_gpio_triggering(bank, offset, trigger); in omap_gpio_unmask_irq()
911 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_unmask_irq()
919 struct gpio_bank *bank = platform_get_drvdata(pdev); in omap_mpuio_suspend_noirq() local
920 void __iomem *mask_reg = bank->base + in omap_mpuio_suspend_noirq()
921 OMAP_MPUIO_GPIO_MASKIT / bank->stride; in omap_mpuio_suspend_noirq()
924 raw_spin_lock_irqsave(&bank->lock, flags); in omap_mpuio_suspend_noirq()
925 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); in omap_mpuio_suspend_noirq()
926 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_mpuio_suspend_noirq()
934 struct gpio_bank *bank = platform_get_drvdata(pdev); in omap_mpuio_resume_noirq() local
935 void __iomem *mask_reg = bank->base + in omap_mpuio_resume_noirq()
936 OMAP_MPUIO_GPIO_MASKIT / bank->stride; in omap_mpuio_resume_noirq()
939 raw_spin_lock_irqsave(&bank->lock, flags); in omap_mpuio_resume_noirq()
940 writel_relaxed(bank->context.wake_en, mask_reg); in omap_mpuio_resume_noirq()
941 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_mpuio_resume_noirq()
968 static inline void omap_mpuio_init(struct gpio_bank *bank) in omap_mpuio_init() argument
970 platform_set_drvdata(&omap_mpuio_device, bank); in omap_mpuio_init()
980 struct gpio_bank *bank; in omap_gpio_get_direction() local
985 bank = gpiochip_get_data(chip); in omap_gpio_get_direction()
986 reg = bank->base + bank->regs->direction; in omap_gpio_get_direction()
987 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_get_direction()
989 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_get_direction()
995 struct gpio_bank *bank; in omap_gpio_input() local
998 bank = gpiochip_get_data(chip); in omap_gpio_input()
999 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_input()
1000 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_input()
1001 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_input()
1007 struct gpio_bank *bank; in omap_gpio_get() local
1009 bank = gpiochip_get_data(chip); in omap_gpio_get()
1011 if (omap_gpio_is_input(bank, offset)) in omap_gpio_get()
1012 return omap_get_gpio_datain(bank, offset); in omap_gpio_get()
1014 return omap_get_gpio_dataout(bank, offset); in omap_gpio_get()
1019 struct gpio_bank *bank; in omap_gpio_output() local
1022 bank = gpiochip_get_data(chip); in omap_gpio_output()
1023 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_output()
1024 bank->set_dataout(bank, offset, value); in omap_gpio_output()
1025 omap_set_gpio_direction(bank, offset, 0); in omap_gpio_output()
1026 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_output()
1033 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_get_multiple() local
1034 void __iomem *reg = bank->base + bank->regs->direction; in omap_gpio_get_multiple()
1041 *bits |= omap_get_gpio_datain_multiple(bank, &l); in omap_gpio_get_multiple()
1045 *bits |= omap_get_gpio_dataout_multiple(bank, &l); in omap_gpio_get_multiple()
1053 struct gpio_bank *bank; in omap_gpio_debounce() local
1057 bank = gpiochip_get_data(chip); in omap_gpio_debounce()
1059 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_debounce()
1060 ret = omap2_set_gpio_debounce(bank, offset, debounce); in omap_gpio_debounce()
1061 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_debounce()
1085 struct gpio_bank *bank; in omap_gpio_set() local
1088 bank = gpiochip_get_data(chip); in omap_gpio_set()
1089 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_set()
1090 bank->set_dataout(bank, offset, value); in omap_gpio_set()
1091 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_set()
1097 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_set_multiple() local
1100 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_set_multiple()
1101 bank->set_dataout_multiple(bank, mask, bits); in omap_gpio_set_multiple()
1102 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_set_multiple()
1107 static void omap_gpio_show_rev(struct gpio_bank *bank) in omap_gpio_show_rev() argument
1112 if (called || bank->regs->revision == USHRT_MAX) in omap_gpio_show_rev()
1115 rev = readw_relaxed(bank->base + bank->regs->revision); in omap_gpio_show_rev()
1122 static void omap_gpio_mod_init(struct gpio_bank *bank) in omap_gpio_mod_init() argument
1124 void __iomem *base = bank->base; in omap_gpio_mod_init()
1127 if (bank->width == 16) in omap_gpio_mod_init()
1130 if (bank->is_mpuio) { in omap_gpio_mod_init()
1131 writel_relaxed(l, bank->base + bank->regs->irqenable); in omap_gpio_mod_init()
1135 omap_gpio_rmw(base, bank->regs->irqenable, l, in omap_gpio_mod_init()
1136 bank->regs->irqenable_inv); in omap_gpio_mod_init()
1137 omap_gpio_rmw(base, bank->regs->irqstatus, l, in omap_gpio_mod_init()
1138 !bank->regs->irqenable_inv); in omap_gpio_mod_init()
1139 if (bank->regs->debounce_en) in omap_gpio_mod_init()
1140 writel_relaxed(0, base + bank->regs->debounce_en); in omap_gpio_mod_init()
1143 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); in omap_gpio_mod_init()
1145 if (bank->regs->ctrl) in omap_gpio_mod_init()
1146 writel_relaxed(0, base + bank->regs->ctrl); in omap_gpio_mod_init()
1149 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) in omap_gpio_chip_init() argument
1161 bank->chip.request = omap_gpio_request; in omap_gpio_chip_init()
1162 bank->chip.free = omap_gpio_free; in omap_gpio_chip_init()
1163 bank->chip.get_direction = omap_gpio_get_direction; in omap_gpio_chip_init()
1164 bank->chip.direction_input = omap_gpio_input; in omap_gpio_chip_init()
1165 bank->chip.get = omap_gpio_get; in omap_gpio_chip_init()
1166 bank->chip.get_multiple = omap_gpio_get_multiple; in omap_gpio_chip_init()
1167 bank->chip.direction_output = omap_gpio_output; in omap_gpio_chip_init()
1168 bank->chip.set_config = omap_gpio_set_config; in omap_gpio_chip_init()
1169 bank->chip.set = omap_gpio_set; in omap_gpio_chip_init()
1170 bank->chip.set_multiple = omap_gpio_set_multiple; in omap_gpio_chip_init()
1171 if (bank->is_mpuio) { in omap_gpio_chip_init()
1172 bank->chip.label = "mpuio"; in omap_gpio_chip_init()
1173 if (bank->regs->wkup_en) in omap_gpio_chip_init()
1174 bank->chip.parent = &omap_mpuio_device.dev; in omap_gpio_chip_init()
1175 bank->chip.base = OMAP_MPUIO(0); in omap_gpio_chip_init()
1177 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", in omap_gpio_chip_init()
1178 gpio, gpio + bank->width - 1); in omap_gpio_chip_init()
1181 bank->chip.label = label; in omap_gpio_chip_init()
1182 bank->chip.base = gpio; in omap_gpio_chip_init()
1184 bank->chip.ngpio = bank->width; in omap_gpio_chip_init()
1191 irq_base = devm_irq_alloc_descs(bank->chip.parent, in omap_gpio_chip_init()
1192 -1, 0, bank->width, 0); in omap_gpio_chip_init()
1194 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); in omap_gpio_chip_init()
1200 if (bank->is_mpuio) { in omap_gpio_chip_init()
1202 if (!bank->regs->wkup_en) in omap_gpio_chip_init()
1206 irq = &bank->chip.irq; in omap_gpio_chip_init()
1211 irq->parents = &bank->irq; in omap_gpio_chip_init()
1214 ret = gpiochip_add_data(&bank->chip, bank); in omap_gpio_chip_init()
1216 dev_err(bank->chip.parent, in omap_gpio_chip_init()
1221 ret = devm_request_irq(bank->chip.parent, bank->irq, in omap_gpio_chip_init()
1223 0, dev_name(bank->chip.parent), bank); in omap_gpio_chip_init()
1225 gpiochip_remove(&bank->chip); in omap_gpio_chip_init()
1227 if (!bank->is_mpuio) in omap_gpio_chip_init()
1228 gpio += bank->width; in omap_gpio_chip_init()
1242 struct gpio_bank *bank; in omap_gpio_probe() local
1252 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); in omap_gpio_probe()
1253 if (!bank) in omap_gpio_probe()
1272 bank->irq = platform_get_irq(pdev, 0); in omap_gpio_probe()
1273 if (bank->irq <= 0) { in omap_gpio_probe()
1274 if (!bank->irq) in omap_gpio_probe()
1275 bank->irq = -ENXIO; in omap_gpio_probe()
1276 if (bank->irq != -EPROBE_DEFER) in omap_gpio_probe()
1278 "can't get irq resource ret=%d\n", bank->irq); in omap_gpio_probe()
1279 return bank->irq; in omap_gpio_probe()
1282 bank->chip.parent = dev; in omap_gpio_probe()
1283 bank->chip.owner = THIS_MODULE; in omap_gpio_probe()
1284 bank->dbck_flag = pdata->dbck_flag; in omap_gpio_probe()
1285 bank->stride = pdata->bank_stride; in omap_gpio_probe()
1286 bank->width = pdata->bank_width; in omap_gpio_probe()
1287 bank->is_mpuio = pdata->is_mpuio; in omap_gpio_probe()
1288 bank->non_wakeup_gpios = pdata->non_wakeup_gpios; in omap_gpio_probe()
1289 bank->regs = pdata->regs; in omap_gpio_probe()
1291 bank->chip.of_node = of_node_get(node); in omap_gpio_probe()
1295 bank->loses_context = true; in omap_gpio_probe()
1297 bank->loses_context = pdata->loses_context; in omap_gpio_probe()
1299 if (bank->loses_context) in omap_gpio_probe()
1300 bank->get_context_loss_count = in omap_gpio_probe()
1304 if (bank->regs->set_dataout && bank->regs->clr_dataout) { in omap_gpio_probe()
1305 bank->set_dataout = omap_set_gpio_dataout_reg; in omap_gpio_probe()
1306 bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple; in omap_gpio_probe()
1308 bank->set_dataout = omap_set_gpio_dataout_mask; in omap_gpio_probe()
1309 bank->set_dataout_multiple = in omap_gpio_probe()
1313 raw_spin_lock_init(&bank->lock); in omap_gpio_probe()
1314 raw_spin_lock_init(&bank->wa_lock); in omap_gpio_probe()
1318 bank->base = devm_ioremap_resource(dev, res); in omap_gpio_probe()
1319 if (IS_ERR(bank->base)) { in omap_gpio_probe()
1320 return PTR_ERR(bank->base); in omap_gpio_probe()
1323 if (bank->dbck_flag) { in omap_gpio_probe()
1324 bank->dbck = devm_clk_get(dev, "dbclk"); in omap_gpio_probe()
1325 if (IS_ERR(bank->dbck)) { in omap_gpio_probe()
1328 bank->dbck_flag = false; in omap_gpio_probe()
1330 clk_prepare(bank->dbck); in omap_gpio_probe()
1334 platform_set_drvdata(pdev, bank); in omap_gpio_probe()
1340 if (bank->is_mpuio) in omap_gpio_probe()
1341 omap_mpuio_init(bank); in omap_gpio_probe()
1343 omap_gpio_mod_init(bank); in omap_gpio_probe()
1345 ret = omap_gpio_chip_init(bank, irqc); in omap_gpio_probe()
1349 if (bank->dbck_flag) in omap_gpio_probe()
1350 clk_unprepare(bank->dbck); in omap_gpio_probe()
1354 omap_gpio_show_rev(bank); in omap_gpio_probe()
1358 list_add_tail(&bank->node, &omap_gpio_list); in omap_gpio_probe()
1365 struct gpio_bank *bank = platform_get_drvdata(pdev); in omap_gpio_remove() local
1367 list_del(&bank->node); in omap_gpio_remove()
1368 gpiochip_remove(&bank->chip); in omap_gpio_remove()
1370 if (bank->dbck_flag) in omap_gpio_remove()
1371 clk_unprepare(bank->dbck); in omap_gpio_remove()
1379 static void omap_gpio_restore_context(struct gpio_bank *bank);
1384 struct gpio_bank *bank = platform_get_drvdata(pdev); in omap_gpio_runtime_suspend() local
1389 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_runtime_suspend()
1400 * by writing back the values saved in bank->context. in omap_gpio_runtime_suspend()
1402 wake_low = bank->context.leveldetect0 & bank->context.wake_en; in omap_gpio_runtime_suspend()
1404 writel_relaxed(wake_low | bank->context.fallingdetect, in omap_gpio_runtime_suspend()
1405 bank->base + bank->regs->fallingdetect); in omap_gpio_runtime_suspend()
1406 wake_hi = bank->context.leveldetect1 & bank->context.wake_en; in omap_gpio_runtime_suspend()
1408 writel_relaxed(wake_hi | bank->context.risingdetect, in omap_gpio_runtime_suspend()
1409 bank->base + bank->regs->risingdetect); in omap_gpio_runtime_suspend()
1411 if (!bank->enabled_non_wakeup_gpios) in omap_gpio_runtime_suspend()
1414 if (bank->power_mode != OFF_MODE) { in omap_gpio_runtime_suspend()
1415 bank->power_mode = 0; in omap_gpio_runtime_suspend()
1423 bank->saved_datain = readl_relaxed(bank->base + in omap_gpio_runtime_suspend()
1424 bank->regs->datain); in omap_gpio_runtime_suspend()
1425 l1 = bank->context.fallingdetect; in omap_gpio_runtime_suspend()
1426 l2 = bank->context.risingdetect; in omap_gpio_runtime_suspend()
1428 l1 &= ~bank->enabled_non_wakeup_gpios; in omap_gpio_runtime_suspend()
1429 l2 &= ~bank->enabled_non_wakeup_gpios; in omap_gpio_runtime_suspend()
1431 writel_relaxed(l1, bank->base + bank->regs->fallingdetect); in omap_gpio_runtime_suspend()
1432 writel_relaxed(l2, bank->base + bank->regs->risingdetect); in omap_gpio_runtime_suspend()
1434 bank->workaround_enabled = true; in omap_gpio_runtime_suspend()
1437 if (bank->get_context_loss_count) in omap_gpio_runtime_suspend()
1438 bank->context_loss_count = in omap_gpio_runtime_suspend()
1439 bank->get_context_loss_count(dev); in omap_gpio_runtime_suspend()
1441 omap_gpio_dbck_disable(bank); in omap_gpio_runtime_suspend()
1442 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_suspend()
1452 struct gpio_bank *bank = platform_get_drvdata(pdev); in omap_gpio_runtime_resume() local
1457 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_runtime_resume()
1464 if (bank->loses_context && !bank->context_valid) { in omap_gpio_runtime_resume()
1465 omap_gpio_init_context(bank); in omap_gpio_runtime_resume()
1467 if (bank->get_context_loss_count) in omap_gpio_runtime_resume()
1468 bank->context_loss_count = in omap_gpio_runtime_resume()
1469 bank->get_context_loss_count(dev); in omap_gpio_runtime_resume()
1472 omap_gpio_dbck_enable(bank); in omap_gpio_runtime_resume()
1480 writel_relaxed(bank->context.fallingdetect, in omap_gpio_runtime_resume()
1481 bank->base + bank->regs->fallingdetect); in omap_gpio_runtime_resume()
1482 writel_relaxed(bank->context.risingdetect, in omap_gpio_runtime_resume()
1483 bank->base + bank->regs->risingdetect); in omap_gpio_runtime_resume()
1485 if (bank->loses_context) { in omap_gpio_runtime_resume()
1486 if (!bank->get_context_loss_count) { in omap_gpio_runtime_resume()
1487 omap_gpio_restore_context(bank); in omap_gpio_runtime_resume()
1489 c = bank->get_context_loss_count(dev); in omap_gpio_runtime_resume()
1490 if (c != bank->context_loss_count) { in omap_gpio_runtime_resume()
1491 omap_gpio_restore_context(bank); in omap_gpio_runtime_resume()
1493 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_resume()
1499 if (!bank->workaround_enabled) { in omap_gpio_runtime_resume()
1500 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_resume()
1504 l = readl_relaxed(bank->base + bank->regs->datain); in omap_gpio_runtime_resume()
1512 l ^= bank->saved_datain; in omap_gpio_runtime_resume()
1513 l &= bank->enabled_non_wakeup_gpios; in omap_gpio_runtime_resume()
1519 gen0 = l & bank->context.fallingdetect; in omap_gpio_runtime_resume()
1520 gen0 &= bank->saved_datain; in omap_gpio_runtime_resume()
1522 gen1 = l & bank->context.risingdetect; in omap_gpio_runtime_resume()
1523 gen1 &= ~(bank->saved_datain); in omap_gpio_runtime_resume()
1526 gen = l & (~(bank->context.fallingdetect) & in omap_gpio_runtime_resume()
1527 ~(bank->context.risingdetect)); in omap_gpio_runtime_resume()
1534 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_gpio_runtime_resume()
1535 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_gpio_runtime_resume()
1537 if (!bank->regs->irqstatus_raw0) { in omap_gpio_runtime_resume()
1538 writel_relaxed(old0 | gen, bank->base + in omap_gpio_runtime_resume()
1539 bank->regs->leveldetect0); in omap_gpio_runtime_resume()
1540 writel_relaxed(old1 | gen, bank->base + in omap_gpio_runtime_resume()
1541 bank->regs->leveldetect1); in omap_gpio_runtime_resume()
1544 if (bank->regs->irqstatus_raw0) { in omap_gpio_runtime_resume()
1545 writel_relaxed(old0 | l, bank->base + in omap_gpio_runtime_resume()
1546 bank->regs->leveldetect0); in omap_gpio_runtime_resume()
1547 writel_relaxed(old1 | l, bank->base + in omap_gpio_runtime_resume()
1548 bank->regs->leveldetect1); in omap_gpio_runtime_resume()
1550 writel_relaxed(old0, bank->base + bank->regs->leveldetect0); in omap_gpio_runtime_resume()
1551 writel_relaxed(old1, bank->base + bank->regs->leveldetect1); in omap_gpio_runtime_resume()
1554 bank->workaround_enabled = false; in omap_gpio_runtime_resume()
1555 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_resume()
1564 struct gpio_bank *bank; in omap2_gpio_prepare_for_idle() local
1566 list_for_each_entry(bank, &omap_gpio_list, node) { in omap2_gpio_prepare_for_idle()
1567 if (!BANK_USED(bank) || !bank->loses_context) in omap2_gpio_prepare_for_idle()
1570 bank->power_mode = pwr_mode; in omap2_gpio_prepare_for_idle()
1572 pm_runtime_put_sync_suspend(bank->chip.parent); in omap2_gpio_prepare_for_idle()
1578 struct gpio_bank *bank; in omap2_gpio_resume_after_idle() local
1580 list_for_each_entry(bank, &omap_gpio_list, node) { in omap2_gpio_resume_after_idle()
1581 if (!BANK_USED(bank) || !bank->loses_context) in omap2_gpio_resume_after_idle()
1584 pm_runtime_get_sync(bank->chip.parent); in omap2_gpio_resume_after_idle()
1613 static void omap_gpio_restore_context(struct gpio_bank *bank) in omap_gpio_restore_context() argument
1615 writel_relaxed(bank->context.wake_en, in omap_gpio_restore_context()
1616 bank->base + bank->regs->wkup_en); in omap_gpio_restore_context()
1617 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); in omap_gpio_restore_context()
1618 writel_relaxed(bank->context.leveldetect0, in omap_gpio_restore_context()
1619 bank->base + bank->regs->leveldetect0); in omap_gpio_restore_context()
1620 writel_relaxed(bank->context.leveldetect1, in omap_gpio_restore_context()
1621 bank->base + bank->regs->leveldetect1); in omap_gpio_restore_context()
1622 writel_relaxed(bank->context.risingdetect, in omap_gpio_restore_context()
1623 bank->base + bank->regs->risingdetect); in omap_gpio_restore_context()
1624 writel_relaxed(bank->context.fallingdetect, in omap_gpio_restore_context()
1625 bank->base + bank->regs->fallingdetect); in omap_gpio_restore_context()
1626 if (bank->regs->set_dataout && bank->regs->clr_dataout) in omap_gpio_restore_context()
1627 writel_relaxed(bank->context.dataout, in omap_gpio_restore_context()
1628 bank->base + bank->regs->set_dataout); in omap_gpio_restore_context()
1630 writel_relaxed(bank->context.dataout, in omap_gpio_restore_context()
1631 bank->base + bank->regs->dataout); in omap_gpio_restore_context()
1632 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); in omap_gpio_restore_context()
1634 if (bank->dbck_enable_mask) { in omap_gpio_restore_context()
1635 writel_relaxed(bank->context.debounce, bank->base + in omap_gpio_restore_context()
1636 bank->regs->debounce); in omap_gpio_restore_context()
1637 writel_relaxed(bank->context.debounce_en, in omap_gpio_restore_context()
1638 bank->base + bank->regs->debounce_en); in omap_gpio_restore_context()
1641 writel_relaxed(bank->context.irqenable1, in omap_gpio_restore_context()
1642 bank->base + bank->regs->irqenable); in omap_gpio_restore_context()
1643 writel_relaxed(bank->context.irqenable2, in omap_gpio_restore_context()
1644 bank->base + bank->regs->irqenable2); in omap_gpio_restore_context()