Lines Matching +full:lock +full:- +full:offset
53 raw_spinlock_t lock; member
65 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) in pl061_get_direction() argument
69 return !(readb(pl061->base + GPIODIR) & BIT(offset)); in pl061_get_direction()
72 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) in pl061_direction_input() argument
78 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_input()
79 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_input()
80 gpiodir &= ~(BIT(offset)); in pl061_direction_input()
81 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_input()
82 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_input()
87 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, in pl061_direction_output() argument
94 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_output()
95 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); in pl061_direction_output()
96 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_output()
97 gpiodir |= BIT(offset); in pl061_direction_output()
98 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_output()
104 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); in pl061_direction_output()
105 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_output()
110 static int pl061_get_value(struct gpio_chip *gc, unsigned offset) in pl061_get_value() argument
114 return !!readb(pl061->base + (BIT(offset + 2))); in pl061_get_value()
117 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) in pl061_set_value() argument
121 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); in pl061_set_value()
128 int offset = irqd_to_hwirq(d); in pl061_irq_type() local
131 u8 bit = BIT(offset); in pl061_irq_type()
133 if (offset < 0 || offset >= PL061_GPIO_NR) in pl061_irq_type()
134 return -EINVAL; in pl061_irq_type()
139 dev_err(gc->parent, in pl061_irq_type()
142 offset); in pl061_irq_type()
143 return -EINVAL; in pl061_irq_type()
147 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_irq_type()
149 gpioiev = readb(pl061->base + GPIOIEV); in pl061_irq_type()
150 gpiois = readb(pl061->base + GPIOIS); in pl061_irq_type()
151 gpioibe = readb(pl061->base + GPIOIBE); in pl061_irq_type()
166 dev_dbg(gc->parent, "line %d: IRQ on %s level\n", in pl061_irq_type()
167 offset, in pl061_irq_type()
175 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); in pl061_irq_type()
190 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", in pl061_irq_type()
191 offset, in pl061_irq_type()
199 dev_warn(gc->parent, "no trigger selected for line %d\n", in pl061_irq_type()
200 offset); in pl061_irq_type()
203 writeb(gpiois, pl061->base + GPIOIS); in pl061_irq_type()
204 writeb(gpioibe, pl061->base + GPIOIBE); in pl061_irq_type()
205 writeb(gpioiev, pl061->base + GPIOIEV); in pl061_irq_type()
207 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_irq_type()
215 int offset; in pl061_irq_handler() local
222 pending = readb(pl061->base + GPIOMIS); in pl061_irq_handler()
224 for_each_set_bit(offset, &pending, PL061_GPIO_NR) in pl061_irq_handler()
225 generic_handle_irq(irq_find_mapping(gc->irq.domain, in pl061_irq_handler()
226 offset)); in pl061_irq_handler()
239 raw_spin_lock(&pl061->lock); in pl061_irq_mask()
240 gpioie = readb(pl061->base + GPIOIE) & ~mask; in pl061_irq_mask()
241 writeb(gpioie, pl061->base + GPIOIE); in pl061_irq_mask()
242 raw_spin_unlock(&pl061->lock); in pl061_irq_mask()
252 raw_spin_lock(&pl061->lock); in pl061_irq_unmask()
253 gpioie = readb(pl061->base + GPIOIE) | mask; in pl061_irq_unmask()
254 writeb(gpioie, pl061->base + GPIOIE); in pl061_irq_unmask()
255 raw_spin_unlock(&pl061->lock); in pl061_irq_unmask()
259 * pl061_irq_ack() - ACK an edge IRQ
263 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
272 raw_spin_lock(&pl061->lock); in pl061_irq_ack()
273 writeb(mask, pl061->base + GPIOIC); in pl061_irq_ack()
274 raw_spin_unlock(&pl061->lock); in pl061_irq_ack()
282 return irq_set_irq_wake(pl061->parent_irq, state); in pl061_irq_set_wake()
287 struct device *dev = &adev->dev; in pl061_probe()
293 return -ENOMEM; in pl061_probe()
295 pl061->base = devm_ioremap_resource(dev, &adev->res); in pl061_probe()
296 if (IS_ERR(pl061->base)) in pl061_probe()
297 return PTR_ERR(pl061->base); in pl061_probe()
299 raw_spin_lock_init(&pl061->lock); in pl061_probe()
300 if (of_property_read_bool(dev->of_node, "gpio-ranges")) { in pl061_probe()
301 pl061->gc.request = gpiochip_generic_request; in pl061_probe()
302 pl061->gc.free = gpiochip_generic_free; in pl061_probe()
305 pl061->gc.base = -1; in pl061_probe()
306 pl061->gc.get_direction = pl061_get_direction; in pl061_probe()
307 pl061->gc.direction_input = pl061_direction_input; in pl061_probe()
308 pl061->gc.direction_output = pl061_direction_output; in pl061_probe()
309 pl061->gc.get = pl061_get_value; in pl061_probe()
310 pl061->gc.set = pl061_set_value; in pl061_probe()
311 pl061->gc.ngpio = PL061_GPIO_NR; in pl061_probe()
312 pl061->gc.label = dev_name(dev); in pl061_probe()
313 pl061->gc.parent = dev; in pl061_probe()
314 pl061->gc.owner = THIS_MODULE; in pl061_probe()
316 ret = gpiochip_add_data(&pl061->gc, pl061); in pl061_probe()
323 pl061->irq_chip.name = dev_name(dev); in pl061_probe()
324 pl061->irq_chip.irq_ack = pl061_irq_ack; in pl061_probe()
325 pl061->irq_chip.irq_mask = pl061_irq_mask; in pl061_probe()
326 pl061->irq_chip.irq_unmask = pl061_irq_unmask; in pl061_probe()
327 pl061->irq_chip.irq_set_type = pl061_irq_type; in pl061_probe()
328 pl061->irq_chip.irq_set_wake = pl061_irq_set_wake; in pl061_probe()
330 writeb(0, pl061->base + GPIOIE); /* disable irqs */ in pl061_probe()
331 irq = adev->irq[0]; in pl061_probe()
333 dev_err(&adev->dev, "invalid IRQ\n"); in pl061_probe()
334 return -ENODEV; in pl061_probe()
336 pl061->parent_irq = irq; in pl061_probe()
338 ret = gpiochip_irqchip_add(&pl061->gc, &pl061->irq_chip, in pl061_probe()
342 dev_info(&adev->dev, "could not add irqchip\n"); in pl061_probe()
345 gpiochip_set_chained_irqchip(&pl061->gc, &pl061->irq_chip, in pl061_probe()
349 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n", in pl061_probe()
350 &adev->res.start); in pl061_probe()
359 int offset; in pl061_suspend() local
361 pl061->csave_regs.gpio_data = 0; in pl061_suspend()
362 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); in pl061_suspend()
363 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); in pl061_suspend()
364 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); in pl061_suspend()
365 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); in pl061_suspend()
366 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); in pl061_suspend()
368 for (offset = 0; offset < PL061_GPIO_NR; offset++) { in pl061_suspend()
369 if (pl061->csave_regs.gpio_dir & (BIT(offset))) in pl061_suspend()
370 pl061->csave_regs.gpio_data |= in pl061_suspend()
371 pl061_get_value(&pl061->gc, offset) << offset; in pl061_suspend()
380 int offset; in pl061_resume() local
382 for (offset = 0; offset < PL061_GPIO_NR; offset++) { in pl061_resume()
383 if (pl061->csave_regs.gpio_dir & (BIT(offset))) in pl061_resume()
384 pl061_direction_output(&pl061->gc, offset, in pl061_resume()
385 pl061->csave_regs.gpio_data & in pl061_resume()
386 (BIT(offset))); in pl061_resume()
388 pl061_direction_input(&pl061->gc, offset); in pl061_resume()
391 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); in pl061_resume()
392 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); in pl061_resume()
393 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); in pl061_resume()
394 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); in pl061_resume()