241 	u16 mask;  in vr41xx_set_irq_trigger()  local
244 		mask = 1 << pin;  in vr41xx_set_irq_trigger()
246 			giu_set(GIUINTTYPL, mask);  in vr41xx_set_irq_trigger()
248 				giu_set(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
250 				giu_clear(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
254 					giu_set(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
255 					giu_clear(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
258 					giu_clear(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
259 					giu_set(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
262 					giu_set(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
263 					giu_set(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
271 			giu_clear(GIUINTTYPL, mask);  in vr41xx_set_irq_trigger()
272 			giu_clear(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
277 		giu_write(GIUINTSTATL, mask);  in vr41xx_set_irq_trigger()
279 		mask = 1 << (pin - GIUINT_HIGH_OFFSET);  in vr41xx_set_irq_trigger()
281 			giu_set(GIUINTTYPH, mask);  in vr41xx_set_irq_trigger()
283 				giu_set(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
285 				giu_clear(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
289 					giu_set(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
290 					giu_clear(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
293 					giu_clear(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
294 					giu_set(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
297 					giu_set(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
298 					giu_set(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
306 			giu_clear(GIUINTTYPH, mask);  in vr41xx_set_irq_trigger()
307 			giu_clear(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
312 		giu_write(GIUINTSTATH, mask);  in vr41xx_set_irq_trigger()
319 	u16 mask;  in vr41xx_set_irq_level()  local
322 		mask = 1 << pin;  in vr41xx_set_irq_level()
324 			giu_set(GIUINTALSELL, mask);  in vr41xx_set_irq_level()
326 			giu_clear(GIUINTALSELL, mask);  in vr41xx_set_irq_level()
327 		giu_write(GIUINTSTATL, mask);  in vr41xx_set_irq_level()
329 		mask = 1 << (pin - GIUINT_HIGH_OFFSET);  in vr41xx_set_irq_level()
331 			giu_set(GIUINTALSELH, mask);  in vr41xx_set_irq_level()
333 			giu_clear(GIUINTALSELH, mask);  in vr41xx_set_irq_level()
334 		giu_write(GIUINTSTATH, mask);  in vr41xx_set_irq_level()
341 	u16 offset, mask, reg;  in giu_set_direction()  local
349 		mask = 1 << pin;  in giu_set_direction()
352 		mask = 1 << (pin - 16);  in giu_set_direction()
356 			mask = 1 << (pin - 32);  in giu_set_direction()
361 				mask = PIOEN0;  in giu_set_direction()
365 				mask = PIOEN1;  in giu_set_direction()
377 		reg |= mask;  in giu_set_direction()
379 		reg &= ~mask;  in giu_set_direction()
389 	u16 reg, mask;  in vr41xx_gpio_pullupdown()  local
398 	mask = 1 << pin;  in vr41xx_gpio_pullupdown()
405 			reg |= mask;  in vr41xx_gpio_pullupdown()
407 			reg &= ~mask;  in vr41xx_gpio_pullupdown()
411 		reg |= mask;  in vr41xx_gpio_pullupdown()
415 		reg &= ~mask;  in vr41xx_gpio_pullupdown()
427 	u16 reg, mask;  in vr41xx_gpio_get()  local
434 		mask = 1 << pin;  in vr41xx_gpio_get()
437 		mask = 1 << (pin - 16);  in vr41xx_gpio_get()
440 		mask = 1 << (pin - 32);  in vr41xx_gpio_get()
443 		mask = 1 << (pin - 48);  in vr41xx_gpio_get()
446 	if (reg & mask)  in vr41xx_gpio_get()
455 	u16 offset, mask, reg;  in vr41xx_gpio_set()  local
463 		mask = 1 << pin;  in vr41xx_gpio_set()
466 		mask = 1 << (pin - 16);  in vr41xx_gpio_set()
469 		mask = 1 << (pin - 32);  in vr41xx_gpio_set()
472 		mask = 1 << (pin - 48);  in vr41xx_gpio_set()
479 		reg |= mask;  in vr41xx_gpio_set()
481 		reg &= ~mask;  in vr41xx_gpio_set()