Lines Matching +full:bank +full:- +full:number
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
23 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
65 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) argument
66 /* MSW Mask & Data -WO */
67 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) argument
68 /* Data Register-RW */
69 #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK)) argument
70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) argument
71 /* Direction mode reg-RW */
72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) argument
73 /* Output enable reg-RW */
74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) argument
75 /* Interrupt mask reg-RO */
76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) argument
77 /* Interrupt enable reg-WO */
78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) argument
79 /* Interrupt disable reg-WO */
80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) argument
81 /* Interrupt status reg-RO */
82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) argument
83 /* Interrupt type reg-RW */
84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) argument
85 /* Interrupt polarity reg-RW */
86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) argument
87 /* Interrupt on any, reg-RW */
88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) argument
93 /* Mid pin number of a bank */
116 * struct zynq_gpio - gpio device private data structure
134 * struct zynq_platform_data - zynq gpio platform data structure
135 * @label: string to store in gpio->label
137 * @ngpio: max number of gpio pins
138 * @max_bank: maximum number of gpio banks
139 * @bank_min: this array represents bank's min pin
140 * @bank_max: this array represents bank's max pin
155 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
162 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ); in zynq_gpio_is_zynq()
166 * gpio_data_ro_bug - test if HW bug exists or not
173 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG); in gpio_data_ro_bug()
177 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
179 * @pin_num: gpio pin number within the device
180 * @bank_num: an output parameter used to return the bank number of the gpio
182 * @bank_pin_num: an output parameter used to return pin number within a bank
186 * Returns the bank number and pin offset within the bank.
193 int bank; in zynq_gpio_get_bank_pin() local
195 for (bank = 0; bank < gpio->p_data->max_bank; bank++) { in zynq_gpio_get_bank_pin()
196 if ((pin_num >= gpio->p_data->bank_min[bank]) && in zynq_gpio_get_bank_pin()
197 (pin_num <= gpio->p_data->bank_max[bank])) { in zynq_gpio_get_bank_pin()
198 *bank_num = bank; in zynq_gpio_get_bank_pin()
199 *bank_pin_num = pin_num - in zynq_gpio_get_bank_pin()
200 gpio->p_data->bank_min[bank]; in zynq_gpio_get_bank_pin()
206 WARN(true, "invalid GPIO pin number: %u", pin_num); in zynq_gpio_get_bank_pin()
212 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
214 * @pin: gpio pin number within the device
231 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
234 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
239 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
242 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
247 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
254 * zynq_gpio_set_value - Modify the state of the pin with specified value
256 * @pin: gpio pin number within the device
260 * upper 16 bits) based on the given pin number and sets the state of a
261 * gpio pin to the specified value. The state is either 0 or non-zero.
273 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; in zynq_gpio_set_value()
287 writel_relaxed(state, gpio->base_addr + reg_offset); in zynq_gpio_set_value()
291 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
293 * @pin: gpio pin number within the device
295 * This function uses the read-modify-write sequence to set the direction of
309 * On zynq bank 0 pins 7 and 8 are special and cannot be used in zynq_gpio_dir_in()
314 return -EINVAL; in zynq_gpio_dir_in()
317 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
319 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
325 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
327 * @pin: gpio pin number within the device
346 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
348 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
351 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
353 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
361 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
363 * @pin: gpio pin number within the device
377 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_get_direction()
383 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
386 * This function calculates gpio pin number from irq number and sets the
387 * bit in the Interrupt Disable register of the corresponding bank to disable
396 device_pin_num = irq_data->hwirq; in zynq_gpio_irq_mask()
399 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); in zynq_gpio_irq_mask()
403 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
404 * @irq_data: irq data containing irq number of gpio pin for the interrupt
407 * This function calculates the gpio pin number from irq number and sets the
408 * bit in the Interrupt Enable register of the corresponding bank to enable
417 device_pin_num = irq_data->hwirq; in zynq_gpio_irq_unmask()
420 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); in zynq_gpio_irq_unmask()
424 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
425 * @irq_data: irq data containing irq number of gpio pin for the interrupt
428 * This function calculates gpio pin number from irq number and sets the bit
429 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
437 device_pin_num = irq_data->hwirq; in zynq_gpio_irq_ack()
440 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); in zynq_gpio_irq_ack()
444 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
445 * @irq_data: irq data containing irq number of gpio pin for the interrupt
467 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
468 * @irq_data: irq data containing irq number of gpio pin
471 * This function gets the gpio pin number and its bank from the gpio pin number
475 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
476 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
477 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
478 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
479 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
488 device_pin_num = irq_data->hwirq; in zynq_gpio_set_irq_type()
491 int_type = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
493 int_pol = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
495 int_any = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
526 return -EINVAL; in zynq_gpio_set_irq_type()
530 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
532 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
534 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
553 irq_set_irq_wake(gpio->irq, on); in zynq_gpio_set_wake()
586 unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; in zynq_gpio_handle_bank_irq()
587 struct irq_domain *irqdomain = gpio->chip.irq.domain; in zynq_gpio_handle_bank_irq()
602 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
605 * This function reads the Interrupt Status Register of each bank to get the
606 * gpio pin number which has triggered an interrupt. It then acks the triggered
621 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_irqhandler()
622 int_sts = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
624 int_enb = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
636 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_save_context()
637 gpio->context.datalsw[bank_num] = in zynq_gpio_save_context()
638 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
640 gpio->context.datamsw[bank_num] = in zynq_gpio_save_context()
641 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
643 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
645 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
647 gpio->context.int_type[bank_num] = in zynq_gpio_save_context()
648 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
650 gpio->context.int_polarity[bank_num] = in zynq_gpio_save_context()
651 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
653 gpio->context.int_any[bank_num] = in zynq_gpio_save_context()
654 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
663 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_restore_context()
664 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + in zynq_gpio_restore_context()
666 writel_relaxed(gpio->context.datalsw[bank_num], in zynq_gpio_restore_context()
667 gpio->base_addr + in zynq_gpio_restore_context()
669 writel_relaxed(gpio->context.datamsw[bank_num], in zynq_gpio_restore_context()
670 gpio->base_addr + in zynq_gpio_restore_context()
672 writel_relaxed(gpio->context.dirm[bank_num], in zynq_gpio_restore_context()
673 gpio->base_addr + in zynq_gpio_restore_context()
675 writel_relaxed(gpio->context.int_type[bank_num], in zynq_gpio_restore_context()
676 gpio->base_addr + in zynq_gpio_restore_context()
678 writel_relaxed(gpio->context.int_polarity[bank_num], in zynq_gpio_restore_context()
679 gpio->base_addr + in zynq_gpio_restore_context()
681 writel_relaxed(gpio->context.int_any[bank_num], in zynq_gpio_restore_context()
682 gpio->base_addr + in zynq_gpio_restore_context()
684 writel_relaxed(~(gpio->context.int_en[bank_num]), in zynq_gpio_restore_context()
685 gpio->base_addr + in zynq_gpio_restore_context()
693 struct irq_data *data = irq_get_irq_data(gpio->irq); in zynq_gpio_suspend()
706 struct irq_data *data = irq_get_irq_data(gpio->irq); in zynq_gpio_resume()
723 clk_disable_unprepare(gpio->clk); in zynq_gpio_runtime_suspend()
733 return clk_prepare_enable(gpio->clk); in zynq_gpio_runtime_resume()
740 ret = pm_runtime_get_sync(chip->parent); in zynq_gpio_request()
751 pm_runtime_put(chip->parent); in zynq_gpio_free()
795 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
796 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
802 * zynq_gpio_probe - Initialization method for a zynq_gpio device
820 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in zynq_gpio_probe()
822 return -ENOMEM; in zynq_gpio_probe()
824 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); in zynq_gpio_probe()
826 dev_err(&pdev->dev, "of_match_node() failed\n"); in zynq_gpio_probe()
827 return -EINVAL; in zynq_gpio_probe()
829 gpio->p_data = match->data; in zynq_gpio_probe()
833 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res); in zynq_gpio_probe()
834 if (IS_ERR(gpio->base_addr)) in zynq_gpio_probe()
835 return PTR_ERR(gpio->base_addr); in zynq_gpio_probe()
837 gpio->irq = platform_get_irq(pdev, 0); in zynq_gpio_probe()
838 if (gpio->irq < 0) { in zynq_gpio_probe()
839 dev_err(&pdev->dev, "invalid IRQ\n"); in zynq_gpio_probe()
840 return gpio->irq; in zynq_gpio_probe()
844 chip = &gpio->chip; in zynq_gpio_probe()
845 chip->label = gpio->p_data->label; in zynq_gpio_probe()
846 chip->owner = THIS_MODULE; in zynq_gpio_probe()
847 chip->parent = &pdev->dev; in zynq_gpio_probe()
848 chip->get = zynq_gpio_get_value; in zynq_gpio_probe()
849 chip->set = zynq_gpio_set_value; in zynq_gpio_probe()
850 chip->request = zynq_gpio_request; in zynq_gpio_probe()
851 chip->free = zynq_gpio_free; in zynq_gpio_probe()
852 chip->direction_input = zynq_gpio_dir_in; in zynq_gpio_probe()
853 chip->direction_output = zynq_gpio_dir_out; in zynq_gpio_probe()
854 chip->get_direction = zynq_gpio_get_direction; in zynq_gpio_probe()
855 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); in zynq_gpio_probe()
856 chip->ngpio = gpio->p_data->ngpio; in zynq_gpio_probe()
859 gpio->clk = devm_clk_get(&pdev->dev, NULL); in zynq_gpio_probe()
860 if (IS_ERR(gpio->clk)) { in zynq_gpio_probe()
861 dev_err(&pdev->dev, "input clock not found.\n"); in zynq_gpio_probe()
862 return PTR_ERR(gpio->clk); in zynq_gpio_probe()
864 ret = clk_prepare_enable(gpio->clk); in zynq_gpio_probe()
866 dev_err(&pdev->dev, "Unable to enable clock.\n"); in zynq_gpio_probe()
870 pm_runtime_set_active(&pdev->dev); in zynq_gpio_probe()
871 pm_runtime_enable(&pdev->dev); in zynq_gpio_probe()
872 ret = pm_runtime_get_sync(&pdev->dev); in zynq_gpio_probe()
879 dev_err(&pdev->dev, "Failed to add gpio chip\n"); in zynq_gpio_probe()
884 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) in zynq_gpio_probe()
885 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + in zynq_gpio_probe()
891 dev_err(&pdev->dev, "Failed to add irq chip\n"); in zynq_gpio_probe()
895 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq, in zynq_gpio_probe()
898 pm_runtime_put(&pdev->dev); in zynq_gpio_probe()
905 pm_runtime_put(&pdev->dev); in zynq_gpio_probe()
907 pm_runtime_disable(&pdev->dev); in zynq_gpio_probe()
908 clk_disable_unprepare(gpio->clk); in zynq_gpio_probe()
914 * zynq_gpio_remove - Driver removal function
923 pm_runtime_get_sync(&pdev->dev); in zynq_gpio_remove()
924 gpiochip_remove(&gpio->chip); in zynq_gpio_remove()
925 clk_disable_unprepare(gpio->clk); in zynq_gpio_remove()
926 device_set_wakeup_capable(&pdev->dev, 0); in zynq_gpio_remove()
927 pm_runtime_disable(&pdev->dev); in zynq_gpio_remove()
942 * zynq_gpio_init - Initial driver registration call