Lines Matching +full:0 +full:xd800
27 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
28 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
29 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
30 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
31 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
32 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
33 #define MC_SEQ_MISC0__MT__HBM 0x60000000
34 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
39 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c)
40 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c)
41 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c)
42 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c)
43 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c)
44 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c)
47 #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807)
48 #define HPD1_REGISTER_OFFSET (0x180a - 0x1807)
49 #define HPD2_REGISTER_OFFSET (0x180d - 0x1807)
50 #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807)
51 #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
52 #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
54 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
55 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
59 #define PIPEID(x) ((x) << 0)
64 #define mmCC_DRM_ID_STRAPS 0x1559
65 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
67 #define mmCHUB_CONTROL 0x619
68 #define BYPASS_VM (1 << 0)
70 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
72 #define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02
75 # define CURSOR_MONO 0
79 # define CURSOR_URGENT_ALWAYS 0
85 # define GRPH_DEPTH_8BPP 0
89 # define GRPH_FORMAT_INDEXED 0
91 # define GRPH_FORMAT_ARGB1555 0
98 # define GRPH_FORMAT_ARGB8888 0
106 # define ADDR_SURF_MACRO_TILE_ASPECT_1 0
110 # define GRPH_ARRAY_LINEAR_GENERAL 0
114 # define DISPLAY_MICRO_TILING 0
118 # define GRPH_ENDIAN_NONE 0
122 # define GRPH_RED_SEL_R 0
126 # define GRPH_GREEN_SEL_G 0
130 # define GRPH_BLUE_SEL_B 0
134 # define GRPH_ALPHA_SEL_A 0
138 # define INPUT_GAMMA_USE_LUT 0
143 # define INPUT_CSC_BYPASS 0
147 # define OUTPUT_CSC_BYPASS 0
154 # define DEGAMMA_BYPASS 0
157 # define GAMUT_REMAP_BYPASS 0
162 # define REGAMMA_BYPASS 0
168 # define FMT_CLAMP_6BPC 0
172 # define HDMI_24BIT_DEEP_COLOR 0
175 # define HDMI_ACR_HW 0
182 # define AFMT_AVI_INFO_Y_RGB 0
186 #define NO_AUTO 0
196 # define BANK_WIDTH(x) ((x) << 0)
202 #define MSG_EXIT_RLC_SAFE_MODE 0
207 #define PACKET_TYPE0 0
213 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
214 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
215 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
217 ((reg) & 0xFFFF) | \
218 ((n) & 0x3FFF) << 16)
219 #define CP_PACKET2 0x80000000
220 #define PACKET2_PAD_SHIFT 0
221 #define PACKET2_PAD_MASK (0x3fffffff << 0)
226 (((op) & 0xFF) << 8) | \
227 ((n) & 0x3FFF) << 16)
232 #define PACKET3_NOP 0x10
233 #define PACKET3_SET_BASE 0x11
234 #define PACKET3_BASE_INDEX(x) ((x) << 0)
236 #define PACKET3_CLEAR_STATE 0x12
237 #define PACKET3_INDEX_BUFFER_SIZE 0x13
238 #define PACKET3_DISPATCH_DIRECT 0x15
239 #define PACKET3_DISPATCH_INDIRECT 0x16
240 #define PACKET3_ATOMIC_GDS 0x1D
241 #define PACKET3_ATOMIC_MEM 0x1E
242 #define PACKET3_OCCLUSION_QUERY 0x1F
243 #define PACKET3_SET_PREDICATION 0x20
244 #define PACKET3_REG_RMW 0x21
245 #define PACKET3_COND_EXEC 0x22
246 #define PACKET3_PRED_EXEC 0x23
247 #define PACKET3_DRAW_INDIRECT 0x24
248 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
249 #define PACKET3_INDEX_BASE 0x26
250 #define PACKET3_DRAW_INDEX_2 0x27
251 #define PACKET3_CONTEXT_CONTROL 0x28
252 #define PACKET3_INDEX_TYPE 0x2A
253 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
254 #define PACKET3_DRAW_INDEX_AUTO 0x2D
255 #define PACKET3_NUM_INSTANCES 0x2F
256 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
257 #define PACKET3_INDIRECT_BUFFER_CONST 0x33
258 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
259 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
260 #define PACKET3_DRAW_PREAMBLE 0x36
261 #define PACKET3_WRITE_DATA 0x37
263 /* 0 - register
273 /* 0 - LRU
277 /* 0 - me
281 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
282 #define PACKET3_MEM_SEMAPHORE 0x39
283 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
284 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
285 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
286 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
287 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
288 #define PACKET3_COPY_DW 0x3B
289 #define PACKET3_WAIT_REG_MEM 0x3C
290 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
291 /* 0 - always
300 /* 0 - reg
304 /* 0 - wait_reg_mem
308 /* 0 - me
311 #define PACKET3_INDIRECT_BUFFER 0x3F
315 /* 0 - LRU
319 #define PACKET3_COPY_DATA 0x40
320 #define PACKET3_PFP_SYNC_ME 0x42
321 #define PACKET3_SURFACE_SYNC 0x43
322 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
345 #define PACKET3_COND_WRITE 0x45
346 #define PACKET3_EVENT_WRITE 0x46
347 #define EVENT_TYPE(x) ((x) << 0)
349 /* 0 - any non-TS event
357 #define PACKET3_EVENT_WRITE_EOP 0x47
365 /* 0 - LRU
370 /* 0 - discard
377 /* 0 - none
378 * 1 - interrupt only (DATA_SEL = 0)
382 /* 0 - MC
385 #define PACKET3_EVENT_WRITE_EOS 0x48
386 #define PACKET3_RELEASE_MEM 0x49
387 #define PACKET3_PREAMBLE_CNTL 0x4A
390 #define PACKET3_DMA_DATA 0x50
393 * 3. SRC_ADDR_LO or DATA [31:0]
394 * 4. SRC_ADDR_HI [31:0]
395 * 5. DST_ADDR_LO [31:0]
396 * 6. DST_ADDR_HI [7:0]
397 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
400 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
401 /* 0 - ME
405 /* 0 - LRU
411 /* 0 - DST_ADDR using DAS
416 /* 0 - LRU
422 /* 0 - SRC_ADDR using SAS
431 /* 0 - none
437 /* 0 - none
443 /* 0 - memory
447 /* 0 - memory
453 #define PACKET3_AQUIRE_MEM 0x58
454 #define PACKET3_REWIND 0x59
455 #define PACKET3_LOAD_UCONFIG_REG 0x5E
456 #define PACKET3_LOAD_SH_REG 0x5F
457 #define PACKET3_LOAD_CONFIG_REG 0x60
458 #define PACKET3_LOAD_CONTEXT_REG 0x61
459 #define PACKET3_SET_CONFIG_REG 0x68
460 #define PACKET3_SET_CONFIG_REG_START 0x00002000
461 #define PACKET3_SET_CONFIG_REG_END 0x00002c00
462 #define PACKET3_SET_CONTEXT_REG 0x69
463 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000
464 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400
465 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
466 #define PACKET3_SET_SH_REG 0x76
467 #define PACKET3_SET_SH_REG_START 0x00002c00
468 #define PACKET3_SET_SH_REG_END 0x00003000
469 #define PACKET3_SET_SH_REG_OFFSET 0x77
470 #define PACKET3_SET_QUEUE_REG 0x78
471 #define PACKET3_SET_UCONFIG_REG 0x79
472 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000
473 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400
474 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
475 #define PACKET3_SCRATCH_RAM_READ 0x7E
476 #define PACKET3_LOAD_CONST_RAM 0x80
477 #define PACKET3_WRITE_CONST_RAM 0x81
478 #define PACKET3_DUMP_CONST_RAM 0x83
479 #define PACKET3_INCREMENT_CE_COUNTER 0x84
480 #define PACKET3_INCREMENT_DE_COUNTER 0x85
481 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
482 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
483 #define PACKET3_SWITCH_BUFFER 0x8B
485 /* SDMA - first instance at 0xd000, second at 0xd800 */
486 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
487 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
490 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
491 (((sub_op) & 0xFF) << 8) | \
492 (((op) & 0xFF) << 0))
494 #define SDMA_OPCODE_NOP 0
495 # define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16)
497 # define SDMA_COPY_SUB_OPCODE_LINEAR 0
504 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0
511 /* 0 - increment
515 /* 0 - wait
522 /* 0 - wait_reg_mem
526 /* 0 - always
535 /* 0 = register
541 /* 0 = byte fill
546 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
553 #define VCE_CMD_NO_OP 0x00000000
554 #define VCE_CMD_END 0x00000001
555 #define VCE_CMD_IB 0x00000002
556 #define VCE_CMD_FENCE 0x00000003
557 #define VCE_CMD_TRAP 0x00000004
558 #define VCE_CMD_IB_AUTO 0x00000005
559 #define VCE_CMD_SEMAPHORE 0x00000006
562 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */
569 MTYPE_CACHED = 0,
574 #define RB_MAP_PKR0(x) ((x) << 0)
575 #define RB_MAP_PKR0_MASK (0x3 << 0)
577 #define RB_MAP_PKR1_MASK (0x3 << 2)
579 #define RB_XSEL2_MASK (0x3 << 4)
583 #define PKR_MAP_MASK (0x3 << 8)
585 #define PKR_XSEL_MASK (0x3 << 10)
587 #define PKR_YSEL_MASK (0x3 << 12)
589 #define SC_MAP_MASK (0x3 << 16)
591 #define SC_XSEL_MASK (0x3 << 18)
593 #define SC_YSEL_MASK (0x3 << 20)
595 #define SE_MAP_MASK (0x3 << 24)
597 #define SE_XSEL_MASK (0x3 << 26)
599 #define SE_YSEL_MASK (0x3 << 28)
602 #define SE_PAIR_MAP(x) ((x) << 0)
603 #define SE_PAIR_MAP_MASK (0x3 << 0)
605 #define SE_PAIR_XSEL_MASK (0x3 << 2)
607 #define SE_PAIR_YSEL_MASK (0x3 << 4)