Lines Matching +full:6 +full:- +full:bit
8 * Copyright (C) 2013-2014 Silicon Image, Inc.
38 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
39 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
40 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
41 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
42 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
43 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
44 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
45 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
49 #define BIT_DPD_PWRON_PLL BIT(7)
50 #define BIT_DPD_PDNTX12 BIT(6)
51 #define BIT_DPD_PDNRX12 BIT(5)
52 #define BIT_DPD_OSC_EN BIT(4)
53 #define BIT_DPD_PWRON_HSIC BIT(3)
54 #define BIT_DPD_PDIDCK_N BIT(2)
55 #define BIT_DPD_PD_MHL_CLK_N BIT(1)
59 #define BIT_DCTL_TDM_LCLK_PHASE BIT(7)
60 #define BIT_DCTL_HSIC_CLK_PHASE BIT(6)
61 #define BIT_DCTL_CTS_TCK_PHASE BIT(5)
62 #define BIT_DCTL_EXT_DDC_SEL BIT(4)
63 #define BIT_DCTL_TRANSCODE BIT(3)
64 #define BIT_DCTL_HSIC_RX_STROBE_PHASE BIT(2)
65 #define BIT_DCTL_HSIC_TX_BIST_START_SEL BIT(1)
66 #define BIT_DCTL_TCLKNX_PHASE BIT(0)
70 #define BIT_PWD_SRST_COC_DOC_RST BIT(7)
71 #define BIT_PWD_SRST_CBUS_RST_SW BIT(6)
72 #define BIT_PWD_SRST_CBUS_RST_SW_EN BIT(5)
73 #define BIT_PWD_SRST_MHLFIFO_RST BIT(4)
74 #define BIT_PWD_SRST_CBUS_RST BIT(3)
75 #define BIT_PWD_SRST_SW_RST_AUTO BIT(2)
76 #define BIT_PWD_SRST_HDCP2X_SW_RST BIT(1)
77 #define BIT_PWD_SRST_SW_RST BIT(0)
87 #define BIT_VID_MODE_M1080P BIT(6)
91 #define BIT_VID_OVRRD_PP_AUTO_DISABLE BIT(7)
92 #define BIT_VID_OVRRD_M1080P_OVRRD BIT(6)
93 #define BIT_VID_OVRRD_MINIVSYNC_ON BIT(5)
94 #define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK BIT(4)
95 #define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN BIT(3)
96 #define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD BIT(2)
97 #define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD BIT(0)
127 #define BIT_CTRL1_GPIO_I_8 BIT(5)
128 #define BIT_CTRL1_GPIO_OEN_8 BIT(4)
129 #define BIT_CTRL1_GPIO_I_7 BIT(3)
130 #define BIT_CTRL1_GPIO_OEN_7 BIT(2)
131 #define BIT_CTRL1_GPIO_I_6 BIT(1)
132 #define BIT_CTRL1_GPIO_OEN_6 BIT(0)
136 #define BIT_INT_CTRL_SOFTWARE_WP BIT(7)
137 #define BIT_INT_CTRL_INTR_OD BIT(2)
138 #define BIT_INT_CTRL_INTR_POLARITY BIT(1)
142 #define BIT_INTR_STATE_INTR_STATE BIT(0)
152 #define BIT_DDC_CMD_DONE BIT(3)
168 #define BIT_INTR_SCDT_CHANGE BIT(0)
172 #define BIT_HPD_CTRL_HPD_DS_SIGNAL BIT(7)
173 #define BIT_HPD_CTRL_HPD_OUT_OD_EN BIT(6)
174 #define BIT_HPD_CTRL_HPD_HIGH BIT(5)
175 #define BIT_HPD_CTRL_HPD_OUT_OVR_EN BIT(4)
176 #define BIT_HPD_CTRL_GPIO_I_1 BIT(3)
177 #define BIT_HPD_CTRL_GPIO_OEN_1 BIT(2)
178 #define BIT_HPD_CTRL_GPIO_I_0 BIT(1)
179 #define BIT_HPD_CTRL_GPIO_OEN_0 BIT(0)
183 #define BIT_CTRL_GPIO_I_5 BIT(7)
184 #define BIT_CTRL_GPIO_OEN_5 BIT(6)
185 #define BIT_CTRL_GPIO_I_4 BIT(5)
186 #define BIT_CTRL_GPIO_OEN_4 BIT(4)
187 #define BIT_CTRL_GPIO_I_3 BIT(3)
188 #define BIT_CTRL_GPIO_OEN_3 BIT(2)
189 #define BIT_CTRL_GPIO_I_2 BIT(1)
190 #define BIT_CTRL_GPIO_OEN_2 BIT(0)
203 #define BIT_CEA_NEW_VSI BIT(2)
204 #define BIT_CEA_NEW_AVI BIT(1)
208 #define BIT_TMDS_CCTRL_TMDS_OE BIT(4)
212 #define BIT_TMDS_CTRL4_SCDT_CKDT_SEL BIT(1)
213 #define BIT_TMDS_CTRL4_TX_EN_BY_SCDT BIT(0)
217 #define BIT_RXBIST_VGB_EN BIT(7)
218 #define BIT_TXBIST_VGB_EN BIT(6)
219 #define BIT_BIST_START_SEL BIT(5)
220 #define BIT_BIST_START_BIT BIT(4)
221 #define BIT_BIST_ALWAYS_ON BIT(3)
222 #define BIT_BIST_TRANS BIT(2)
223 #define BIT_BIST_RESET BIT(1)
224 #define BIT_BIST_EN BIT(0)
248 #define BIT_LM_DDC_SW_TPI_EN_DISABLED BIT(7)
250 #define BIT_LM_DDC_VIDEO_MUTE_EN BIT(5)
251 #define BIT_LM_DDC_DDC_TPI_SW BIT(2)
252 #define BIT_LM_DDC_DDC_GRANT BIT(1)
253 #define BIT_LM_DDC_DDC_GPU_REQUEST BIT(0)
257 #define BIT_DDC_MANUAL_MAN_DDC BIT(7)
258 #define BIT_DDC_MANUAL_VP_SEL BIT(6)
259 #define BIT_DDC_MANUAL_DSDA BIT(5)
260 #define BIT_DDC_MANUAL_DSCL BIT(4)
261 #define BIT_DDC_MANUAL_GCP_HW_CTL_EN BIT(3)
262 #define BIT_DDC_MANUAL_DDCM_ABORT_WP BIT(2)
263 #define BIT_DDC_MANUAL_IO_DSDA BIT(1)
264 #define BIT_DDC_MANUAL_IO_DSCL BIT(0)
285 #define BIT_DDC_STATUS_DDC_BUS_LOW BIT(6)
286 #define BIT_DDC_STATUS_DDC_NO_ACK BIT(5)
287 #define BIT_DDC_STATUS_DDC_I2C_IN_PROG BIT(4)
288 #define BIT_DDC_STATUS_DDC_FIFO_FULL BIT(3)
289 #define BIT_DDC_STATUS_DDC_FIFO_EMPTY BIT(2)
290 #define BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE BIT(1)
291 #define BIT_DDC_STATUS_DDC_FIFO_WRITE_IN_USE BIT(0)
295 #define BIT_DDC_CMD_HDCP_DDC_EN BIT(6)
296 #define BIT_DDC_CMD_SDA_DEL_EN BIT(5)
297 #define BIT_DDC_CMD_DDC_FLT_EN BIT(4)
309 #define BIT_DDC_DOUT_CNT_DDC_DELAY_CNT_8 BIT(7)
317 #define BIT_TEST_TXCTRL_RCLK_REF_SEL BIT(7)
318 #define BIT_TEST_TXCTRL_PCLK_REF_SEL BIT(6)
320 #define BIT_TEST_TXCTRL_HDMI_MODE BIT(1)
321 #define BIT_TEST_TXCTRL_TST_PLLCK BIT(0)
326 /* I2C Device Address re-assignment */
334 #define BIT_UTSRST_FC_SRST BIT(5)
335 #define BIT_UTSRST_KEEPER_SRST BIT(4)
336 #define BIT_UTSRST_HTX_SRST BIT(3)
337 #define BIT_UTSRST_TRX_SRST BIT(2)
338 #define BIT_UTSRST_TTX_SRST BIT(1)
339 #define BIT_UTSRST_HRX_SRST BIT(0)
344 #define BIT_HRXCTRL3_HRX_OUT_EN BIT(2)
345 #define BIT_HRXCTRL3_STATUS_EN BIT(1)
346 #define BIT_HRXCTRL3_HRX_STAY_RESET BIT(0)
355 #define BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT BIT(3)
369 #define BIT_TTXINTL_TTX_INTR7 BIT(7)
370 #define BIT_TTXINTL_TTX_INTR6 BIT(6)
371 #define BIT_TTXINTL_TTX_INTR5 BIT(5)
372 #define BIT_TTXINTL_TTX_INTR4 BIT(4)
373 #define BIT_TTXINTL_TTX_INTR3 BIT(3)
374 #define BIT_TTXINTL_TTX_INTR2 BIT(2)
375 #define BIT_TTXINTL_TTX_INTR1 BIT(1)
376 #define BIT_TTXINTL_TTX_INTR0 BIT(0)
380 #define BIT_TTXINTH_TTX_INTR15 BIT(7)
381 #define BIT_TTXINTH_TTX_INTR14 BIT(6)
382 #define BIT_TTXINTH_TTX_INTR13 BIT(5)
383 #define BIT_TTXINTH_TTX_INTR12 BIT(4)
384 #define BIT_TTXINTH_TTX_INTR11 BIT(3)
385 #define BIT_TTXINTH_TTX_INTR10 BIT(2)
386 #define BIT_TTXINTH_TTX_INTR9 BIT(1)
387 #define BIT_TTXINTH_TTX_INTR8 BIT(0)
391 #define BIT_TRXCTRL_TRX_CLR_WVALLOW BIT(4)
392 #define BIT_TRXCTRL_TRX_FROM_SE_COC BIT(3)
414 #define BIT_TDM_INTR_SYNC_DATA BIT(0)
415 #define BIT_TDM_INTR_SYNC_WAIT BIT(1)
422 #define BIT_HTXCTRL_HTX_ALLSBE_SOP BIT(4)
423 #define BIT_HTXCTRL_HTX_RGDINV_USB BIT(3)
424 #define BIT_HTXCTRL_HTX_RSPTDM_BUSY BIT(2)
425 #define BIT_HTXCTRL_HTX_DRVCONN1 BIT(1)
426 #define BIT_HTXCTRL_HTX_DRVRST1 BIT(0)
442 #define BIT_FCGC_HSIC_HOSTMODE BIT(1)
443 #define BIT_FCGC_HSIC_ENABLE BIT(0)
472 #define BIT_TDMLLCTL_TTX_LL_TIE_LOW BIT(1)
473 #define BIT_TDMLLCTL_TTX_LL_SEL_MODE BIT(0)
482 #define BIT_TMDS_CLK_EN_CLK_EN BIT(0)
486 #define BIT_TMDS_CH_EN_CH0_EN BIT(4)
487 #define BIT_TMDS_CH_EN_CH12_EN BIT(0)
491 #define BIT_BGR_BIAS_BGR_EN BIT(7)
499 #define BIT_ALICE0_ZONE_CTRL_ICRST_N BIT(7)
500 #define BIT_ALICE0_ZONE_CTRL_USE_INT_DIV20 BIT(6)
509 /* MHL Tx Control 6th, default value: 0xa0 */
516 #define BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT BIT(7)
517 #define BIT_PKT_FILTER_0_DROP_CEA_CP_PKT BIT(6)
518 #define BIT_PKT_FILTER_0_DROP_MPEG_PKT BIT(5)
519 #define BIT_PKT_FILTER_0_DROP_SPIF_PKT BIT(4)
520 #define BIT_PKT_FILTER_0_DROP_AIF_PKT BIT(3)
521 #define BIT_PKT_FILTER_0_DROP_AVI_PKT BIT(2)
522 #define BIT_PKT_FILTER_0_DROP_CTS_PKT BIT(1)
523 #define BIT_PKT_FILTER_0_DROP_GCP_PKT BIT(0)
527 #define BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS BIT(7)
528 #define BIT_PKT_FILTER_1_AVI_OVERRIDE_DIS BIT(6)
529 #define BIT_PKT_FILTER_1_DROP_AUDIO_PKT BIT(3)
530 #define BIT_PKT_FILTER_1_DROP_GEN2_PKT BIT(2)
531 #define BIT_PKT_FILTER_1_DROP_GEN_PKT BIT(1)
532 #define BIT_PKT_FILTER_1_DROP_VSIF_PKT BIT(0)
536 #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_CLR_MUTE BIT(7)
537 #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_SET_MUTE BIT(6)
538 #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP BIT(5)
539 #define BIT_TMDS_CSTAT_P3_CLR_AVI BIT(3)
540 #define BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS BIT(2)
541 #define BIT_TMDS_CSTAT_P3_SCDT BIT(1)
542 #define BIT_TMDS_CSTAT_P3_CKDT BIT(0)
546 #define BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC BIT(5)
547 #define BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR BIT(4)
548 #define BIT_RX_HDMI_CTRL0_HDMI_MODE_SW_VALUE BIT(3)
549 #define BIT_RX_HDMI_CTRL0_HDMI_MODE_OVERWRITE BIT(2)
550 #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN BIT(1)
551 #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE BIT(0)
557 #define BIT_RX_HDMI_CTRL2_USE_AV_MUTE BIT(3)
558 #define BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI BIT(0)
567 #define BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI BIT(5)
568 #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI BIT(4)
569 #define BIT_RX_HDMI_CLR_BUFFER_VSI_IEEE_ID_CHK_EN BIT(3)
570 #define BIT_RX_HDMI_CLR_BUFFER_SWAP_VSI_IEEE_ID BIT(2)
571 #define BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN BIT(1)
572 #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN BIT(0)
585 #define BIT_INTR9_EDID_ERROR BIT(6)
586 #define BIT_INTR9_EDID_DONE BIT(5)
587 #define BIT_INTR9_DEVCAP_DONE BIT(4)
594 #define BIT_TPI_CBUS_START_RCP_REQ_START BIT(7)
595 #define BIT_TPI_CBUS_START_RCPK_REPLY_START BIT(6)
596 #define BIT_TPI_CBUS_START_RCPE_REPLY_START BIT(5)
597 #define BIT_TPI_CBUS_START_PUT_LINK_MODE_START BIT(4)
598 #define BIT_TPI_CBUS_START_PUT_DCAPCHG_START BIT(3)
599 #define BIT_TPI_CBUS_START_PUT_DCAPRDY_START BIT(2)
600 #define BIT_TPI_CBUS_START_GET_EDID_START_0 BIT(1)
601 #define BIT_TPI_CBUS_START_GET_DEVCAP_START BIT(0)
605 #define BIT_EDID_CTRL_EDID_PRIME_VALID BIT(7)
606 #define BIT_EDID_CTRL_XDEVCAP_EN BIT(6)
607 #define BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP BIT(5)
608 #define BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO BIT(4)
609 #define BIT_EDID_CTRL_EDID_FIFO_ACCESS_ALWAYS_EN BIT(3)
610 #define BIT_EDID_CTRL_EDID_FIFO_BLOCK_SEL BIT(2)
611 #define BIT_EDID_CTRL_INVALID_BKSV BIT(1)
612 #define BIT_EDID_CTRL_EDID_MODE_EN BIT(0)
631 #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_QUARTER_CLK_SEL BIT(6)
632 #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE BIT(5)
633 #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON BIT(4)
634 #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_RUN BIT(3)
635 #define BIT_TX_IP_BIST_CNTLSTA_TXCLK_HALF_SEL BIT(2)
636 #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN BIT(1)
637 #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_SEL BIT(0)
651 /* E-MSC General Control, default value: 0x80 */
653 #define BIT_GENCTL_SPEC_TRANS_DIS BIT(7)
654 #define BIT_GENCTL_DIS_XMIT_ERR_STATE BIT(6)
655 #define BIT_GENCTL_SPI_MISO_EDGE BIT(5)
656 #define BIT_GENCTL_SPI_MOSI_EDGE BIT(4)
657 #define BIT_GENCTL_CLR_EMSC_RFIFO BIT(3)
658 #define BIT_GENCTL_CLR_EMSC_XFIFO BIT(2)
659 #define BIT_GENCTL_START_TRAIN_SEQ BIT(1)
660 #define BIT_GENCTL_EMSC_EN BIT(0)
662 /* E-MSC Comma ErrorCNT, default value: 0x03 */
664 #define BIT_COMMECNT_I2C_TO_EMSC_EN BIT(7)
667 /* E-MSC RFIFO ByteCnt, default value: 0x00 */
676 #define BIT_SPIBURSTSTAT_SPI_HDCPRST BIT(7)
677 #define BIT_SPIBURSTSTAT_SPI_CBUSRST BIT(6)
678 #define BIT_SPIBURSTSTAT_SPI_SRST BIT(5)
679 #define BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE BIT(0)
681 /* E-MSC 1st Interrupt, default value: 0x00 */
683 #define BIT_EMSCINTR_EMSC_XFIFO_EMPTY BIT(7)
684 #define BIT_EMSCINTR_EMSC_XMIT_ACK_TOUT BIT(6)
685 #define BIT_EMSCINTR_EMSC_RFIFO_READ_ERR BIT(5)
686 #define BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR BIT(4)
687 #define BIT_EMSCINTR_EMSC_COMMA_CHAR_ERR BIT(3)
688 #define BIT_EMSCINTR_EMSC_XMIT_DONE BIT(2)
689 #define BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT BIT(1)
690 #define BIT_EMSCINTR_SPI_DVLD BIT(0)
692 /* E-MSC Interrupt Mask, default value: 0x00 */
695 /* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
698 /* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
701 /* E-MSC 2nd Interrupt, default value: 0x00 */
703 #define BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR BIT(0)
705 /* E-MSC Interrupt Mask, default value: 0x00 */
707 #define BIT_EMSCINTRMASK1_EMSC_INTRMASK1_0 BIT(0)
711 #define BIT_MHL_TOP_CTL_MHL3_DOC_SEL BIT(7)
712 #define BIT_MHL_TOP_CTL_MHL_PP_SEL BIT(6)
717 #define BIT_MHL_DP_CTL0_DP_OE BIT(7)
718 #define BIT_MHL_DP_CTL0_TX_OE_OVR BIT(6)
728 #define BIT_MHL_DP_CTL2_CLK_BYPASS_EN BIT(7)
743 /* MHL DataPath 6th Ctl, default value: 0x3f */
745 #define BIT_MHL_DP_CTL5_RSEN_EN_OVR BIT(7)
746 #define BIT_MHL_DP_CTL5_RSEN_EN BIT(6)
753 #define BIT_MHL_PLL_CTL0_AUD_CLK_EN BIT(7)
771 #define BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL BIT(1)
772 #define BIT_MHL_PLL_CTL0_ZONE_MASK_OE BIT(0)
776 #define BIT_MHL_PLL_CTL2_CLKDETECT_EN BIT(7)
777 #define BIT_MHL_PLL_CTL2_MEAS_FVCO BIT(3)
778 #define BIT_MHL_PLL_CTL2_PLL_FAST_LOCK BIT(2)
783 #define BIT_MHL_CBUS_CTL0_CBUS_RGND_TEST_MODE BIT(7)
808 #define BIT_MHL_COC_CTL0_COC_BIAS_EN BIT(7)
814 #define BIT_MHL_COC_CTL1_COC_EN BIT(7)
819 #define BIT_MHL_COC_CTL3_COC_AECHO_EN BIT(0)
826 /* MHL CoC 6th Ctl, default value: 0x0d */
831 #define BIT_MHL_DOC_CTL0_DOC_RXDATA_EN BIT(7)
834 #define BIT_MHL_DOC_CTL0_DOC_RXBIAS_EN BIT(0)
838 #define BIT_MHL_DP_CTL6_DP_TAP2_SGN BIT(5)
839 #define BIT_MHL_DP_CTL6_DP_TAP2_EN BIT(4)
840 #define BIT_MHL_DP_CTL6_DP_TAP1_SGN BIT(3)
841 #define BIT_MHL_DP_CTL6_DP_TAP1_EN BIT(2)
842 #define BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN BIT(1)
843 #define BIT_MHL_DP_CTL6_DP_PRE_POST_SEL BIT(0)
858 #define BIT_MHL3_TX_ZONE_CTL_MHL2_INTPLT_ZONE_MANU_EN BIT(7)
869 #define BIT_HDCP2X_POLL_CS_HDCP2X_MSG_SZ_CLR_OPTION BIT(6)
870 #define BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION BIT(5)
871 #define BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION BIT(4)
873 #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT BIT(1)
874 #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_EN BIT(0)
884 #define BIT_HDCP2X_CTRL_0_HDCP2X_ENCRYPT_EN BIT(7)
885 #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_SEL BIT(6)
886 #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR BIT(5)
887 #define BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE BIT(4)
888 #define BIT_HDCP2X_CTRL_0_HDCP2X_HDMIMODE BIT(3)
889 #define BIT_HDCP2X_CTRL_0_HDCP2X_REPEATER BIT(2)
890 #define BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX BIT(1)
891 #define BIT_HDCP2X_CTRL_0_HDCP2X_EN BIT(0)
896 #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_SW BIT(3)
897 #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_OVR BIT(2)
898 #define BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK BIT(1)
899 #define BIT_HDCP2X_CTRL_1_HDCP2X_REAUTH_SW BIT(0)
903 #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START BIT(4)
904 #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR_START BIT(3)
905 #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR BIT(2)
906 #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START BIT(1)
907 #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD BIT(0)
937 #define BIT_M3_CTRL_H2M_SWRST BIT(4)
938 #define BIT_M3_CTRL_SW_MHL3_SEL BIT(3)
939 #define BIT_M3_CTRL_M3AV_EN BIT(2)
940 #define BIT_M3_CTRL_ENC_TMDS BIT(1)
941 #define BIT_M3_CTRL_MHL3_MASTER_EN BIT(0)
952 #define BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN BIT(4)
953 #define BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN BIT(3)
954 #define BIT_M3_P0CTRL_MHL3_P0_HDCP_EN BIT(2)
955 #define BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED BIT(1)
956 #define BIT_M3_P0CTRL_MHL3_P0_PORT_EN BIT(0)
965 #define BIT_M3_SCTRL_MHL3_SCRAMBLER_EN BIT(0)
1004 #define BIT_TPI_INPUT_EXTENDEDBITMODE BIT(7)
1005 #define BIT_TPI_INPUT_ENDITHER BIT(6)
1011 #define BIT_TPI_OUTPUT_CSCMODE709 BIT(4)
1020 #define BIT_TPI_SC_TPI_UPDATE_FLG BIT(7)
1021 #define BIT_TPI_SC_TPI_REAUTH_CTL BIT(6)
1022 #define BIT_TPI_SC_TPI_OUTPUT_MODE_1 BIT(5)
1023 #define BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN BIT(4)
1024 #define BIT_TPI_SC_TPI_AV_MUTE BIT(3)
1025 #define BIT_TPI_SC_DDC_GPU_REQUEST BIT(2)
1026 #define BIT_TPI_SC_DDC_TPI_SW BIT(1)
1027 #define BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI BIT(0)
1031 #define BIT_TPI_COPP_DATA1_COPP_GPROT BIT(7)
1032 #define BIT_TPI_COPP_DATA1_COPP_LPROT BIT(6)
1038 #define BIT_TPI_COPP_DATA1_COPP_HDCP_REP BIT(3)
1039 #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_0 BIT(2)
1040 #define BIT_TPI_COPP_DATA1_COPP_PROTYPE BIT(1)
1041 #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_1 BIT(0)
1045 #define BIT_TPI_COPP_DATA2_INTR_ENCRYPTION BIT(5)
1046 #define BIT_TPI_COPP_DATA2_KSV_FORWARD BIT(4)
1047 #define BIT_TPI_COPP_DATA2_INTERM_RI_CHECK_EN BIT(3)
1048 #define BIT_TPI_COPP_DATA2_DOUBLE_RI_CHECK BIT(2)
1049 #define BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD BIT(1)
1050 #define BIT_TPI_COPP_DATA2_COPP_PROTLEVEL BIT(0)
1057 #define BIT_TPI_INTR_ST0_TPI_AUTH_CHNGE_STAT BIT(7)
1058 #define BIT_TPI_INTR_ST0_TPI_V_RDY_STAT BIT(6)
1059 #define BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT BIT(5)
1060 #define BIT_TPI_INTR_ST0_KSV_FIFO_FIRST_STAT BIT(3)
1061 #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_DONE_STAT BIT(2)
1062 #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT BIT(1)
1063 #define BIT_TPI_INTR_ST0_READ_BKSV_ERR_STAT BIT(0)
1070 #define BIT_TPI_BSTATUS1_DS_DEV_EXCEED BIT(7)
1076 #define BIT_TPI_BSTATUS2_DS_HDMI_MODE BIT(4)
1077 #define BIT_TPI_BSTATUS2_DS_CASC_EXCEED BIT(3)
1082 #define BIT_TPI_HW_OPT3_DDC_DEBUG BIT(7)
1083 #define BIT_TPI_HW_OPT3_RI_CHECK_SKIP BIT(3)
1084 #define BIT_TPI_HW_OPT3_TPI_DDC_BURST_MODE BIT(2)
1089 #define BIT_TPI_INFO_FSEL_EN BIT(7)
1090 #define BIT_TPI_INFO_FSEL_RPT BIT(6)
1091 #define BIT_TPI_INFO_FSEL_READ_FLAG BIT(5)
1106 #define BIT_COC_STAT_0_PLL_LOCKED BIT(7)
1130 #define BIT_COC_CTL3_COC_CTRL3_7 BIT(7)
1135 #define BIT_COC_CTL6_COC_CTRL6_7 BIT(7)
1136 #define BIT_COC_CTL6_COC_CTRL6_6 BIT(6)
1141 #define BIT_COC_CTL7_COC_CTRL7_7 BIT(7)
1142 #define BIT_COC_CTL7_COC_CTRL7_6 BIT(6)
1143 #define BIT_COC_CTL7_COC_CTRL7_5 BIT(5)
1161 #define BIT_COC_CTLD_COC_CTRLD_7 BIT(7)
1166 #define BIT_COC_CTLE_COC_CTRLE_7 BIT(7)
1186 #define BIT_COC_CTL15_COC_CTRL15_7 BIT(7)
1195 #define BIT_COC_PLL_LOCK_STATUS_CHANGE BIT(0)
1196 #define BIT_COC_CALIBRATION_DONE BIT(1)
1200 #define BIT_COC_MISC_CTL0_FSM_MON BIT(7)
1237 #define BIT_DOC_CTL6_DOC_CTRL6_7 BIT(7)
1238 #define BIT_DOC_CTL6_DOC_CTRL6_6 BIT(6)
1244 #define BIT_DOC_CTL7_DOC_CTRL7_7 BIT(7)
1245 #define BIT_DOC_CTL7_DOC_CTRL7_6 BIT(6)
1246 #define BIT_DOC_CTL7_DOC_CTRL7_5 BIT(5)
1252 #define BIT_DOC_CTL8_DOC_CTRL8_7 BIT(7)
1265 #define BIT_DOC_CTLE_DOC_CTRLE_7 BIT(7)
1266 #define BIT_DOC_CTLE_DOC_CTRLE_6 BIT(6)
1290 #define BIT_MDT_RCV_CTRL_MDT_RCV_EN BIT(7)
1291 #define BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN BIT(6)
1292 #define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN BIT(4)
1293 #define BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN BIT(3)
1294 #define BIT_MDT_RCV_CTRL_MDT_DISABLE BIT(2)
1295 #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL BIT(1)
1296 #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR BIT(0)
1303 #define BIT_MDT_XMIT_CTRL_EN BIT(7)
1304 #define BIT_MDT_XMIT_CTRL_CMD_MERGE_EN BIT(6)
1305 #define BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN BIT(5)
1306 #define BIT_MDT_XMIT_CTRL_FIXED_AID BIT(4)
1307 #define BIT_MDT_XMIT_CTRL_SINGLE_RUN_EN BIT(3)
1308 #define BIT_MDT_XMIT_CTRL_CLR_ABORT_WAIT BIT(2)
1309 #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL BIT(1)
1310 #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_CUR BIT(0)
1323 #define BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN BIT(4)
1328 #define BIT_MDT_RFIFO_DATA_RDY BIT(0)
1329 #define BIT_MDT_IDLE_AFTER_HAWB_DISABLE BIT(2)
1330 #define BIT_MDT_XFIFO_EMPTY BIT(3)
1337 #define BIT_MDT_RCV_TIMEOUT BIT(0)
1338 #define BIT_MDT_RCV_SM_ABORT_PKT_RCVD BIT(1)
1339 #define BIT_MDT_RCV_SM_ERROR BIT(2)
1340 #define BIT_MDT_XMIT_TIMEOUT BIT(5)
1341 #define BIT_MDT_XMIT_SM_ABORT_PKT_RCVD BIT(6)
1342 #define BIT_MDT_XMIT_SM_ERROR BIT(7)
1352 #define BIT_CBUS_STATUS_MHL_CABLE_PRESENT BIT(4)
1353 #define BIT_CBUS_STATUS_MSC_HB_SUCCESS BIT(3)
1354 #define BIT_CBUS_STATUS_CBUS_HPD BIT(2)
1355 #define BIT_CBUS_STATUS_MHL_MODE BIT(1)
1356 #define BIT_CBUS_STATUS_CBUS_CONNECTED BIT(0)
1360 #define BIT_CBUS_MSC_MT_DONE_NACK BIT(7)
1361 #define BIT_CBUS_MSC_MR_SET_INT BIT(6)
1362 #define BIT_CBUS_MSC_MR_WRITE_BURST BIT(5)
1363 #define BIT_CBUS_MSC_MR_MSC_MSG BIT(4)
1364 #define BIT_CBUS_MSC_MR_WRITE_STAT BIT(3)
1365 #define BIT_CBUS_HPD_CHG BIT(2)
1366 #define BIT_CBUS_MSC_MT_DONE BIT(1)
1367 #define BIT_CBUS_CNX_CHG BIT(0)
1374 #define BIT_CBUS_CMD_ABORT BIT(6)
1375 #define BIT_CBUS_MSC_ABORT_RCVD BIT(3)
1376 #define BIT_CBUS_DDC_ABORT BIT(2)
1377 #define BIT_CBUS_CEC_ABORT BIT(1)
1416 #define BIT_MSC_COMMAND_START_DEBUG BIT(5)
1417 #define BIT_MSC_COMMAND_START_WRITE_BURST BIT(4)
1418 #define BIT_MSC_COMMAND_START_WRITE_STAT BIT(3)
1419 #define BIT_MSC_COMMAND_START_READ_DEVCAP BIT(2)
1420 #define BIT_MSC_COMMAND_START_MSC_MSG BIT(1)
1421 #define BIT_MSC_COMMAND_START_PEER BIT(0)
1440 #define BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN BIT(7)
1446 #define BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN BIT(7)
1447 #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS BIT(6)
1448 #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS BIT(5)
1449 #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE BIT(3)
1450 #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE BIT(2)
1456 #define BIT_CBUS3_CNVT_TEARCBUS_EN BIT(1)
1457 #define BIT_CBUS3_CNVT_CBUS3CNVT_EN BIT(0)
1461 #define BIT_DISC_CTRL1_CBUS_INTR_EN BIT(7)
1462 #define BIT_DISC_CTRL1_HB_ONLY BIT(6)
1465 #define BIT_DISC_CTRL1_DISC_EN BIT(0)
1475 #define VAL_DISC_CTRL4(pup_disc, pup_idle) (((pup_disc) << 6) | (pup_idle << 4))
1479 #define BIT_DISC_CTRL5_DSM_OVRIDE BIT(3)
1484 #define BIT_DISC_CTRL8_NOMHLINT_CLR_BYPASS BIT(7)
1485 #define BIT_DISC_CTRL8_DELAY_CBUS_INTR_EN BIT(0)
1489 #define BIT_DISC_CTRL9_MHL3_RSEN_BYP BIT(7)
1490 #define BIT_DISC_CTRL9_MHL3DISC_EN BIT(6)
1491 #define BIT_DISC_CTRL9_WAKE_DRVFLT BIT(4)
1492 #define BIT_DISC_CTRL9_NOMHL_EST BIT(3)
1493 #define BIT_DISC_CTRL9_DISC_PULSE_PROCEED BIT(2)
1494 #define BIT_DISC_CTRL9_WAKE_PULSE_BYPASS BIT(1)
1495 #define BIT_DISC_CTRL9_VBUS_OUTPUT_CAPABILITY_SRC BIT(0)
1499 #define BIT_DISC_STAT1_PSM_OVRIDE BIT(5)
1504 #define BIT_DISC_STAT2_CBUS_OE_POL BIT(6)
1505 #define BIT_DISC_STAT2_CBUS_SATUS BIT(5)
1506 #define BIT_DISC_STAT2_RSEN BIT(4)
1522 #define BIT_RGND_READY_INT BIT(6)
1523 #define BIT_CBUS_MHL12_DISCON_INT BIT(5)
1524 #define BIT_CBUS_MHL3_DISCON_INT BIT(4)
1525 #define BIT_NOT_MHL_EST_INT BIT(3)
1526 #define BIT_MHL_EST_INT BIT(2)
1527 #define BIT_MHL3_EST_INT BIT(1)