Lines Matching +full:dp +full:- +full:phy1
52 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
84 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
151 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
154 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
239 ret = regmap_write(tc->regmap, reg, var); \
245 ret = regmap_read(tc->regmap, reg, var); \
272 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT); in tc_poll_timeout()
277 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0, in tc_aux_wait_busy()
286 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value); in tc_aux_get_status()
291 dev_err(tc->dev, "i2c access timeout!\n"); in tc_aux_get_status()
292 return -ETIMEDOUT; in tc_aux_get_status()
294 return -EBUSY; in tc_aux_get_status()
305 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); in tc_aux_transfer()
306 u8 request = msg->request & ~DP_AUX_I2C_MOT; in tc_aux_transfer()
307 u8 *buf = msg->buffer; in tc_aux_transfer()
328 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp); in tc_aux_transfer()
334 return -EINVAL; in tc_aux_transfer()
338 tc_write(DP0_AUXADDR, msg->address); in tc_aux_transfer()
340 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request); in tc_aux_transfer()
346 ret = tc_aux_get_status(tc, &msg->reply); in tc_aux_transfer()
392 if (tc->link.scrambler_dis) in tc_srcctrl()
394 if (tc->link.coding8b10b) in tc_srcctrl()
397 if (tc->link.spread) in tc_srcctrl()
399 if (tc->link.base.num_lanes == 2) in tc_srcctrl()
401 if (tc->link.base.rate != 162000) in tc_srcctrl()
424 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, in tc_pxl_pll_en()
458 delta = clk - pixelclock; in tc_pxl_pll_en()
472 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", in tc_pxl_pll_en()
474 return -EINVAL; in tc_pxl_pll_en()
477 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, in tc_pxl_pll_en()
479 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, in tc_pxl_pll_en()
496 (ext_div[best_pre] << 20) | /* External Pre-divider */ in tc_pxl_pll_en()
497 (ext_div[best_post] << 16) | /* External Post-divider */ in tc_pxl_pll_en()
515 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); in tc_pxl_pll_dis()
550 rate = clk_get_rate(tc->refclk); in tc_aux_link_setup()
565 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); in tc_aux_link_setup()
566 return -EINVAL; in tc_aux_link_setup()
569 /* Setup DP-PHY / PLL */ in tc_aux_link_setup()
574 if (tc->link.base.num_lanes == 2) in tc_aux_link_setup()
588 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, in tc_aux_link_setup()
590 if (ret == -ETIMEDOUT) { in tc_aux_link_setup()
591 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); in tc_aux_link_setup()
603 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); in tc_aux_link_setup()
613 /* Read DP Rx Link Capability */ in tc_get_display_props()
614 ret = drm_dp_link_probe(&tc->aux, &tc->link.base); in tc_get_display_props()
617 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) { in tc_get_display_props()
618 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); in tc_get_display_props()
619 tc->link.base.rate = 270000; in tc_get_display_props()
622 if (tc->link.base.num_lanes > 2) { in tc_get_display_props()
623 dev_dbg(tc->dev, "Falling to 2 lanes\n"); in tc_get_display_props()
624 tc->link.base.num_lanes = 2; in tc_get_display_props()
627 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp); in tc_get_display_props()
630 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */ in tc_get_display_props()
632 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp); in tc_get_display_props()
635 tc->link.coding8b10b = tmp[0] & BIT(0); in tc_get_display_props()
636 tc->link.scrambler_dis = 0; in tc_get_display_props()
638 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp); in tc_get_display_props()
641 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; in tc_get_display_props()
643 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", in tc_get_display_props()
644 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, in tc_get_display_props()
645 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps", in tc_get_display_props()
646 tc->link.base.num_lanes, in tc_get_display_props()
647 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? in tc_get_display_props()
648 "enhanced" : "non-enhanced"); in tc_get_display_props()
649 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b); in tc_get_display_props()
650 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", in tc_get_display_props()
651 tc->link.assr, tc->assr); in tc_get_display_props()
656 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); in tc_get_display_props()
666 int left_margin = mode->htotal - mode->hsync_end; in tc_set_video_mode()
667 int right_margin = mode->hsync_start - mode->hdisplay; in tc_set_video_mode()
668 int hsync_len = mode->hsync_end - mode->hsync_start; in tc_set_video_mode()
669 int upper_margin = mode->vtotal - mode->vsync_end; in tc_set_video_mode()
670 int lower_margin = mode->vsync_start - mode->vdisplay; in tc_set_video_mode()
671 int vsync_len = mode->vsync_end - mode->vsync_start; in tc_set_video_mode()
679 max_tu_symbol = TU_SIZE_RECOMMENDED - 1; in tc_set_video_mode()
681 dev_dbg(tc->dev, "set mode %dx%d\n", in tc_set_video_mode()
682 mode->hdisplay, mode->vdisplay); in tc_set_video_mode()
683 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", in tc_set_video_mode()
685 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", in tc_set_video_mode()
687 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); in tc_set_video_mode()
701 (ALIGN(mode->hdisplay, 2) << 0)); /* width */ in tc_set_video_mode()
705 (mode->vdisplay << 0)); /* height */ in tc_set_video_mode()
717 /* DP Main Stream Attributes */ in tc_set_video_mode()
718 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; in tc_set_video_mode()
723 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal)); in tc_set_video_mode()
729 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay)); in tc_set_video_mode()
732 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) | in tc_set_video_mode()
733 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0)); in tc_set_video_mode()
785 } while ((!(value & LT_LOOPDONE)) && (--timeout)); in tc_link_training()
787 dev_err(tc->dev, "Link training timeout!\n"); in tc_link_training()
792 dev_dbg(tc->dev, in tc_link_training()
794 pattern, 1000 - timeout, errors[error]); in tc_link_training()
802 if ((tc->link.base.num_lanes == 2) && in tc_link_training()
808 if ((tc->link.base.num_lanes == 1) && in tc_link_training()
817 } while (--retry); in tc_link_training()
819 dev_err(tc->dev, "Failed to finish training phase %d\n", in tc_link_training()
830 struct drm_dp_aux *aux = &tc->aux; in tc_main_link_setup()
831 struct device *dev = tc->dev; in tc_main_link_setup()
840 if (!tc->mode) in tc_main_link_setup()
841 return -EINVAL; in tc_main_link_setup()
846 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | in tc_main_link_setup()
847 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); in tc_main_link_setup()
849 rate = clk_get_rate(tc->refclk); in tc_main_link_setup()
864 return -EINVAL; in tc_main_link_setup()
871 if (tc->link.base.num_lanes == 2) in tc_main_link_setup()
885 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_main_link_setup()
886 1000 * tc->mode->clock); in tc_main_link_setup()
902 } while ((!(value & PHY_RDY)) && (--timeout)); in tc_main_link_setup()
906 return -ETIMEDOUT; in tc_main_link_setup()
910 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); in tc_main_link_setup()
921 if (tc->assr != tc->link.assr) { in tc_main_link_setup()
923 tc->assr); in tc_main_link_setup()
925 tmp[0] = tc->assr; in tc_main_link_setup()
934 if (tmp[0] != tc->assr) { in tc_main_link_setup()
936 tc->assr); in tc_main_link_setup()
938 tc->link.scrambler_dis = 1; in tc_main_link_setup()
943 ret = drm_dp_link_configure(aux, &tc->link.base); in tc_main_link_setup()
948 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; in tc_main_link_setup()
950 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00; in tc_main_link_setup()
965 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; in tc_main_link_setup()
977 /* Read DPCD 0x202-0x207 */ in tc_main_link_setup()
981 } while ((--timeout) && in tc_main_link_setup()
982 !(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes))); in tc_main_link_setup()
985 /* Read DPCD 0x200-0x201 */ in tc_main_link_setup()
1000 return -EAGAIN; in tc_main_link_setup()
1003 ret = tc_set_video_mode(tc, tc->mode); in tc_main_link_setup()
1014 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); in tc_main_link_setup()
1017 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); in tc_main_link_setup()
1027 dev_dbg(tc->dev, "stream: %d\n", state); in tc_main_link_stream()
1031 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) in tc_main_link_stream()
1064 drm_panel_prepare(tc->panel); in tc_bridge_pre_enable()
1074 dev_err(tc->dev, "main link setup error: %d\n", ret); in tc_bridge_enable()
1080 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_bridge_enable()
1084 drm_panel_enable(tc->panel); in tc_bridge_enable()
1092 drm_panel_disable(tc->panel); in tc_bridge_disable()
1096 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_bridge_disable()
1103 drm_panel_unprepare(tc->panel); in tc_bridge_post_disable()
1111 adj->flags = mode->flags; in tc_bridge_mode_fixup()
1112 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); in tc_bridge_mode_fixup()
1113 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); in tc_bridge_mode_fixup()
1126 if (mode->clock > 154000) in tc_connector_mode_valid()
1129 req = mode->clock * bits_per_pixel / 8; in tc_connector_mode_valid()
1130 avail = tc->link.base.num_lanes * tc->link.base.rate; in tc_connector_mode_valid()
1144 tc->mode = mode; in tc_bridge_mode_set()
1156 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_connector_get_modes()
1160 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) { in tc_connector_get_modes()
1161 count = tc->panel->funcs->get_modes(tc->panel); in tc_connector_get_modes()
1166 edid = drm_get_edid(connector, &tc->aux.ddc); in tc_connector_get_modes()
1168 kfree(tc->edid); in tc_connector_get_modes()
1169 tc->edid = edid; in tc_connector_get_modes()
1183 connector->polled = DRM_CONNECTOR_POLL_CONNECT | in tc_connector_set_polling()
1192 return tc->bridge.encoder; in tc_connector_best_encoder()
1213 struct drm_device *drm = bridge->dev; in tc_bridge_attach()
1217 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); in tc_bridge_attach()
1218 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, in tc_bridge_attach()
1223 if (tc->panel) in tc_bridge_attach()
1224 drm_panel_attach(tc->panel, &tc->connector); in tc_bridge_attach()
1226 drm_display_info_set_bus_formats(&tc->connector.display_info, in tc_bridge_attach()
1228 tc->connector.display_info.bus_flags = in tc_bridge_attach()
1232 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); in tc_bridge_attach()
1288 struct device *dev = &client->dev; in tc_probe()
1294 return -ENOMEM; in tc_probe()
1296 tc->dev = dev; in tc_probe()
1299 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL); in tc_probe()
1300 if (ret && ret != -ENODEV) in tc_probe()
1304 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); in tc_probe()
1305 if (IS_ERR(tc->sd_gpio)) in tc_probe()
1306 return PTR_ERR(tc->sd_gpio); in tc_probe()
1308 if (tc->sd_gpio) { in tc_probe()
1309 gpiod_set_value_cansleep(tc->sd_gpio, 0); in tc_probe()
1314 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); in tc_probe()
1315 if (IS_ERR(tc->reset_gpio)) in tc_probe()
1316 return PTR_ERR(tc->reset_gpio); in tc_probe()
1318 if (tc->reset_gpio) { in tc_probe()
1319 gpiod_set_value_cansleep(tc->reset_gpio, 1); in tc_probe()
1323 tc->refclk = devm_clk_get(dev, "ref"); in tc_probe()
1324 if (IS_ERR(tc->refclk)) { in tc_probe()
1325 ret = PTR_ERR(tc->refclk); in tc_probe()
1330 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); in tc_probe()
1331 if (IS_ERR(tc->regmap)) { in tc_probe()
1332 ret = PTR_ERR(tc->regmap); in tc_probe()
1337 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); in tc_probe()
1339 dev_err(tc->dev, "can not read device ID: %d\n", ret); in tc_probe()
1343 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { in tc_probe()
1344 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); in tc_probe()
1345 return -EINVAL; in tc_probe()
1348 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ in tc_probe()
1354 /* Register DP AUX channel */ in tc_probe()
1355 tc->aux.name = "TC358767 AUX i2c adapter"; in tc_probe()
1356 tc->aux.dev = tc->dev; in tc_probe()
1357 tc->aux.transfer = tc_aux_transfer; in tc_probe()
1358 ret = drm_dp_aux_register(&tc->aux); in tc_probe()
1366 tc_connector_set_polling(tc, &tc->connector); in tc_probe()
1368 tc->bridge.funcs = &tc_bridge_funcs; in tc_probe()
1369 tc->bridge.of_node = dev->of_node; in tc_probe()
1370 drm_bridge_add(&tc->bridge); in tc_probe()
1376 drm_dp_aux_unregister(&tc->aux); in tc_probe()
1384 drm_bridge_remove(&tc->bridge); in tc_remove()
1385 drm_dp_aux_unregister(&tc->aux); in tc_remove()