Lines Matching full:gpu
29 { .name = "etnaviv-gpu,2d" },
37 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
41 *value = gpu->identity.model; in etnaviv_gpu_get_param()
45 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
49 *value = gpu->identity.features; in etnaviv_gpu_get_param()
53 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
57 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
73 *value = gpu->identity.minor_features5; in etnaviv_gpu_get_param()
77 *value = gpu->identity.minor_features6; in etnaviv_gpu_get_param()
81 *value = gpu->identity.minor_features7; in etnaviv_gpu_get_param()
85 *value = gpu->identity.minor_features8; in etnaviv_gpu_get_param()
89 *value = gpu->identity.minor_features9; in etnaviv_gpu_get_param()
93 *value = gpu->identity.minor_features10; in etnaviv_gpu_get_param()
97 *value = gpu->identity.minor_features11; in etnaviv_gpu_get_param()
101 *value = gpu->identity.stream_count; in etnaviv_gpu_get_param()
105 *value = gpu->identity.register_max; in etnaviv_gpu_get_param()
109 *value = gpu->identity.thread_count; in etnaviv_gpu_get_param()
113 *value = gpu->identity.vertex_cache_size; in etnaviv_gpu_get_param()
117 *value = gpu->identity.shader_core_count; in etnaviv_gpu_get_param()
121 *value = gpu->identity.pixel_pipes; in etnaviv_gpu_get_param()
125 *value = gpu->identity.vertex_output_buffer_size; in etnaviv_gpu_get_param()
129 *value = gpu->identity.buffer_size; in etnaviv_gpu_get_param()
133 *value = gpu->identity.instruction_count; in etnaviv_gpu_get_param()
137 *value = gpu->identity.num_constants; in etnaviv_gpu_get_param()
141 *value = gpu->identity.varyings_count; in etnaviv_gpu_get_param()
145 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); in etnaviv_gpu_get_param()
153 #define etnaviv_is_model_rev(gpu, mod, rev) \ argument
154 ((gpu)->identity.model == chipModel_##mod && \
155 (gpu)->identity.revision == rev)
159 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) in etnaviv_hw_specs() argument
161 if (gpu->identity.minor_features0 & in etnaviv_hw_specs()
166 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
167 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
168 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
169 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
171 gpu->identity.stream_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
173 gpu->identity.register_max = etnaviv_field(specs[0], in etnaviv_hw_specs()
175 gpu->identity.thread_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
177 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], in etnaviv_hw_specs()
179 gpu->identity.shader_core_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
181 gpu->identity.pixel_pipes = etnaviv_field(specs[0], in etnaviv_hw_specs()
183 gpu->identity.vertex_output_buffer_size = in etnaviv_hw_specs()
187 gpu->identity.buffer_size = etnaviv_field(specs[1], in etnaviv_hw_specs()
189 gpu->identity.instruction_count = etnaviv_field(specs[1], in etnaviv_hw_specs()
191 gpu->identity.num_constants = etnaviv_field(specs[1], in etnaviv_hw_specs()
194 gpu->identity.varyings_count = etnaviv_field(specs[2], in etnaviv_hw_specs()
201 gpu->identity.stream_count = streams; in etnaviv_hw_specs()
205 if (gpu->identity.stream_count == 0) { in etnaviv_hw_specs()
206 if (gpu->identity.model >= 0x1000) in etnaviv_hw_specs()
207 gpu->identity.stream_count = 4; in etnaviv_hw_specs()
209 gpu->identity.stream_count = 1; in etnaviv_hw_specs()
213 if (gpu->identity.register_max) in etnaviv_hw_specs()
214 gpu->identity.register_max = 1 << gpu->identity.register_max; in etnaviv_hw_specs()
215 else if (gpu->identity.model == chipModel_GC400) in etnaviv_hw_specs()
216 gpu->identity.register_max = 32; in etnaviv_hw_specs()
218 gpu->identity.register_max = 64; in etnaviv_hw_specs()
221 if (gpu->identity.thread_count) in etnaviv_hw_specs()
222 gpu->identity.thread_count = 1 << gpu->identity.thread_count; in etnaviv_hw_specs()
223 else if (gpu->identity.model == chipModel_GC400) in etnaviv_hw_specs()
224 gpu->identity.thread_count = 64; in etnaviv_hw_specs()
225 else if (gpu->identity.model == chipModel_GC500 || in etnaviv_hw_specs()
226 gpu->identity.model == chipModel_GC530) in etnaviv_hw_specs()
227 gpu->identity.thread_count = 128; in etnaviv_hw_specs()
229 gpu->identity.thread_count = 256; in etnaviv_hw_specs()
231 if (gpu->identity.vertex_cache_size == 0) in etnaviv_hw_specs()
232 gpu->identity.vertex_cache_size = 8; in etnaviv_hw_specs()
234 if (gpu->identity.shader_core_count == 0) { in etnaviv_hw_specs()
235 if (gpu->identity.model >= 0x1000) in etnaviv_hw_specs()
236 gpu->identity.shader_core_count = 2; in etnaviv_hw_specs()
238 gpu->identity.shader_core_count = 1; in etnaviv_hw_specs()
241 if (gpu->identity.pixel_pipes == 0) in etnaviv_hw_specs()
242 gpu->identity.pixel_pipes = 1; in etnaviv_hw_specs()
245 if (gpu->identity.vertex_output_buffer_size) { in etnaviv_hw_specs()
246 gpu->identity.vertex_output_buffer_size = in etnaviv_hw_specs()
247 1 << gpu->identity.vertex_output_buffer_size; in etnaviv_hw_specs()
248 } else if (gpu->identity.model == chipModel_GC400) { in etnaviv_hw_specs()
249 if (gpu->identity.revision < 0x4000) in etnaviv_hw_specs()
250 gpu->identity.vertex_output_buffer_size = 512; in etnaviv_hw_specs()
251 else if (gpu->identity.revision < 0x4200) in etnaviv_hw_specs()
252 gpu->identity.vertex_output_buffer_size = 256; in etnaviv_hw_specs()
254 gpu->identity.vertex_output_buffer_size = 128; in etnaviv_hw_specs()
256 gpu->identity.vertex_output_buffer_size = 512; in etnaviv_hw_specs()
259 switch (gpu->identity.instruction_count) { in etnaviv_hw_specs()
261 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || in etnaviv_hw_specs()
262 gpu->identity.model == chipModel_GC880) in etnaviv_hw_specs()
263 gpu->identity.instruction_count = 512; in etnaviv_hw_specs()
265 gpu->identity.instruction_count = 256; in etnaviv_hw_specs()
269 gpu->identity.instruction_count = 1024; in etnaviv_hw_specs()
273 gpu->identity.instruction_count = 2048; in etnaviv_hw_specs()
277 gpu->identity.instruction_count = 256; in etnaviv_hw_specs()
281 if (gpu->identity.num_constants == 0) in etnaviv_hw_specs()
282 gpu->identity.num_constants = 168; in etnaviv_hw_specs()
284 if (gpu->identity.varyings_count == 0) { in etnaviv_hw_specs()
285 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) in etnaviv_hw_specs()
286 gpu->identity.varyings_count = 12; in etnaviv_hw_specs()
288 gpu->identity.varyings_count = 8; in etnaviv_hw_specs()
295 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || in etnaviv_hw_specs()
296 etnaviv_is_model_rev(gpu, GC4000, 0x5222) || in etnaviv_hw_specs()
297 etnaviv_is_model_rev(gpu, GC4000, 0x5245) || in etnaviv_hw_specs()
298 etnaviv_is_model_rev(gpu, GC4000, 0x5208) || in etnaviv_hw_specs()
299 etnaviv_is_model_rev(gpu, GC3000, 0x5435) || in etnaviv_hw_specs()
300 etnaviv_is_model_rev(gpu, GC2200, 0x5244) || in etnaviv_hw_specs()
301 etnaviv_is_model_rev(gpu, GC2100, 0x5108) || in etnaviv_hw_specs()
302 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || in etnaviv_hw_specs()
303 etnaviv_is_model_rev(gpu, GC1500, 0x5246) || in etnaviv_hw_specs()
304 etnaviv_is_model_rev(gpu, GC880, 0x5107) || in etnaviv_hw_specs()
305 etnaviv_is_model_rev(gpu, GC880, 0x5106)) in etnaviv_hw_specs()
306 gpu->identity.varyings_count -= 1; in etnaviv_hw_specs()
309 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) in etnaviv_hw_identify() argument
313 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
317 gpu->identity.model = chipModel_GC500; in etnaviv_hw_identify()
318 gpu->identity.revision = etnaviv_field(chipIdentity, in etnaviv_hw_identify()
322 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
323 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
331 if ((gpu->identity.model & 0xff00) == 0x0400 && in etnaviv_hw_identify()
332 gpu->identity.model != chipModel_GC420) { in etnaviv_hw_identify()
333 gpu->identity.model = gpu->identity.model & 0x0400; in etnaviv_hw_identify()
337 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { in etnaviv_hw_identify()
338 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
339 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); in etnaviv_hw_identify()
346 gpu->identity.revision = 0x1051; in etnaviv_hw_identify()
351 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in in etnaviv_hw_identify()
357 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { in etnaviv_hw_identify()
358 gpu->identity.model = chipModel_GC3000; in etnaviv_hw_identify()
359 gpu->identity.revision &= 0xffff; in etnaviv_hw_identify()
363 dev_info(gpu->dev, "model: GC%x, revision: %x\n", in etnaviv_hw_identify()
364 gpu->identity.model, gpu->identity.revision); in etnaviv_hw_identify()
370 if (etnaviv_fill_identity_from_hwdb(gpu)) in etnaviv_hw_identify()
373 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); in etnaviv_hw_identify()
376 if (gpu->identity.model == chipModel_GC700) in etnaviv_hw_identify()
377 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; in etnaviv_hw_identify()
379 if ((gpu->identity.model == chipModel_GC500 && in etnaviv_hw_identify()
380 gpu->identity.revision < 2) || in etnaviv_hw_identify()
381 (gpu->identity.model == chipModel_GC300 && in etnaviv_hw_identify()
382 gpu->identity.revision < 0x2000)) { in etnaviv_hw_identify()
388 gpu->identity.minor_features0 = 0; in etnaviv_hw_identify()
389 gpu->identity.minor_features1 = 0; in etnaviv_hw_identify()
390 gpu->identity.minor_features2 = 0; in etnaviv_hw_identify()
391 gpu->identity.minor_features3 = 0; in etnaviv_hw_identify()
392 gpu->identity.minor_features4 = 0; in etnaviv_hw_identify()
393 gpu->identity.minor_features5 = 0; in etnaviv_hw_identify()
395 gpu->identity.minor_features0 = in etnaviv_hw_identify()
396 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); in etnaviv_hw_identify()
398 if (gpu->identity.minor_features0 & in etnaviv_hw_identify()
400 gpu->identity.minor_features1 = in etnaviv_hw_identify()
401 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); in etnaviv_hw_identify()
402 gpu->identity.minor_features2 = in etnaviv_hw_identify()
403 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); in etnaviv_hw_identify()
404 gpu->identity.minor_features3 = in etnaviv_hw_identify()
405 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); in etnaviv_hw_identify()
406 gpu->identity.minor_features4 = in etnaviv_hw_identify()
407 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); in etnaviv_hw_identify()
408 gpu->identity.minor_features5 = in etnaviv_hw_identify()
409 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); in etnaviv_hw_identify()
413 if (gpu->identity.model == chipModel_GC600) { in etnaviv_hw_identify()
414 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | in etnaviv_hw_identify()
423 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; in etnaviv_hw_identify()
426 etnaviv_hw_specs(gpu); in etnaviv_hw_identify()
429 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) in etnaviv_gpu_load_clock() argument
431 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
433 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
436 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) in etnaviv_gpu_update_clock() argument
438 if (gpu->identity.minor_features2 & in etnaviv_gpu_update_clock()
440 clk_set_rate(gpu->clk_core, in etnaviv_gpu_update_clock()
441 gpu->base_rate_core >> gpu->freq_scale); in etnaviv_gpu_update_clock()
442 clk_set_rate(gpu->clk_shader, in etnaviv_gpu_update_clock()
443 gpu->base_rate_shader >> gpu->freq_scale); in etnaviv_gpu_update_clock()
445 unsigned int fscale = 1 << (6 - gpu->freq_scale); in etnaviv_gpu_update_clock()
446 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_gpu_update_clock()
450 etnaviv_gpu_load_clock(gpu, clock); in etnaviv_gpu_update_clock()
454 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) in etnaviv_hw_reset() argument
460 /* We hope that the GPU resets in under one second */ in etnaviv_hw_reset()
465 unsigned int fscale = 1 << (6 - gpu->freq_scale); in etnaviv_hw_reset()
467 etnaviv_gpu_load_clock(gpu, control); in etnaviv_hw_reset()
469 /* isolate the GPU. */ in etnaviv_hw_reset()
471 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
473 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_hw_reset()
474 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
479 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
487 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
489 /* reset GPU isolation. */ in etnaviv_hw_reset()
491 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
494 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
498 dev_dbg(gpu->dev, "FE is not idle\n"); in etnaviv_hw_reset()
503 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
505 /* is the GPU idle? */ in etnaviv_hw_reset()
508 dev_dbg(gpu->dev, "GPU is not idle\n"); in etnaviv_hw_reset()
514 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
521 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
522 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
524 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", in etnaviv_hw_reset()
532 /* We rely on the GPU running, so program the clock */ in etnaviv_hw_reset()
533 etnaviv_gpu_update_clock(gpu); in etnaviv_hw_reset()
538 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) in etnaviv_gpu_enable_mlcg() argument
543 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg()
547 if (gpu->identity.revision == 0x4301 || in etnaviv_gpu_enable_mlcg()
548 gpu->identity.revision == 0x4302) in etnaviv_gpu_enable_mlcg()
551 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); in etnaviv_gpu_enable_mlcg()
553 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); in etnaviv_gpu_enable_mlcg()
556 if (gpu->identity.model >= chipModel_GC400 && in etnaviv_gpu_enable_mlcg()
557 gpu->identity.model != chipModel_GC420 && in etnaviv_gpu_enable_mlcg()
558 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) in etnaviv_gpu_enable_mlcg()
565 if (gpu->identity.revision < 0x5000 && in etnaviv_gpu_enable_mlcg()
566 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && in etnaviv_gpu_enable_mlcg()
567 !(gpu->identity.minor_features1 & in etnaviv_gpu_enable_mlcg()
571 if (gpu->identity.revision < 0x5422) in etnaviv_gpu_enable_mlcg()
575 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || in etnaviv_gpu_enable_mlcg()
576 etnaviv_is_model_rev(gpu, GC2000, 0x5108)) in etnaviv_gpu_enable_mlcg()
582 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); in etnaviv_gpu_enable_mlcg()
585 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) in etnaviv_gpu_start_fe() argument
587 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
588 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
592 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_gpu_start_fe()
593 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
599 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) in etnaviv_gpu_setup_pulse_eater() argument
607 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || in etnaviv_gpu_setup_pulse_eater()
608 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { in etnaviv_gpu_setup_pulse_eater()
613 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || in etnaviv_gpu_setup_pulse_eater()
614 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { in etnaviv_gpu_setup_pulse_eater()
619 if ((gpu->identity.revision > 0x5420) && in etnaviv_gpu_setup_pulse_eater()
620 (gpu->identity.features & chipFeatures_PIPE_3D)) in etnaviv_gpu_setup_pulse_eater()
623 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); in etnaviv_gpu_setup_pulse_eater()
627 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); in etnaviv_gpu_setup_pulse_eater()
630 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_init() argument
634 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || in etnaviv_gpu_hw_init()
635 etnaviv_is_model_rev(gpu, GC320, 0x5220)) && in etnaviv_gpu_hw_init()
636 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { in etnaviv_gpu_hw_init()
639 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; in etnaviv_gpu_hw_init()
641 if (gpu->identity.revision == 0x5007) in etnaviv_gpu_hw_init()
646 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); in etnaviv_gpu_hw_init()
650 etnaviv_gpu_enable_mlcg(gpu); in etnaviv_gpu_hw_init()
653 * Update GPU AXI cache atttribute to "cacheable, no allocate". in etnaviv_gpu_hw_init()
656 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
661 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { in etnaviv_gpu_hw_init()
662 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); in etnaviv_gpu_hw_init()
667 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); in etnaviv_gpu_hw_init()
670 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_gpu_hw_init()
671 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); in etnaviv_gpu_hw_init()
673 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); in etnaviv_gpu_hw_init()
677 etnaviv_gpu_setup_pulse_eater(gpu); in etnaviv_gpu_hw_init()
680 etnaviv_iommu_restore(gpu); in etnaviv_gpu_hw_init()
683 prefetch = etnaviv_buffer_init(gpu); in etnaviv_gpu_hw_init()
685 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); in etnaviv_gpu_hw_init()
686 etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer), in etnaviv_gpu_hw_init()
690 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) in etnaviv_gpu_init() argument
694 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_init()
696 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); in etnaviv_gpu_init()
700 etnaviv_hw_identify(gpu); in etnaviv_gpu_init()
702 if (gpu->identity.model == 0) { in etnaviv_gpu_init()
703 dev_err(gpu->dev, "Unknown GPU model\n"); in etnaviv_gpu_init()
709 if (gpu->identity.features & chipFeatures_PIPE_VG && in etnaviv_gpu_init()
710 gpu->identity.features & chipFeatures_FE20) { in etnaviv_gpu_init()
711 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); in etnaviv_gpu_init()
717 * Set the GPU linear window to be at the end of the DMA window, where in etnaviv_gpu_init()
725 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || in etnaviv_gpu_init()
726 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { in etnaviv_gpu_init()
727 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); in etnaviv_gpu_init()
729 gpu->memory_base = PHYS_OFFSET; in etnaviv_gpu_init()
731 gpu->memory_base = dma_mask - SZ_2G + 1; in etnaviv_gpu_init()
733 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); in etnaviv_gpu_init()
734 gpu->memory_base = PHYS_OFFSET; in etnaviv_gpu_init()
735 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; in etnaviv_gpu_init()
742 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && in etnaviv_gpu_init()
743 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) in etnaviv_gpu_init()
744 gpu->sec_mode = ETNA_SEC_KERNEL; in etnaviv_gpu_init()
746 ret = etnaviv_hw_reset(gpu); in etnaviv_gpu_init()
748 dev_err(gpu->dev, "GPU reset failed\n"); in etnaviv_gpu_init()
752 gpu->mmu = etnaviv_iommu_new(gpu); in etnaviv_gpu_init()
753 if (IS_ERR(gpu->mmu)) { in etnaviv_gpu_init()
754 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n"); in etnaviv_gpu_init()
755 ret = PTR_ERR(gpu->mmu); in etnaviv_gpu_init()
759 gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu); in etnaviv_gpu_init()
760 if (IS_ERR(gpu->cmdbuf_suballoc)) { in etnaviv_gpu_init()
761 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n"); in etnaviv_gpu_init()
762 ret = PTR_ERR(gpu->cmdbuf_suballoc); in etnaviv_gpu_init()
767 ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer, in etnaviv_gpu_init()
770 dev_err(gpu->dev, "could not create command buffer\n"); in etnaviv_gpu_init()
774 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 && in etnaviv_gpu_init()
775 etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) { in etnaviv_gpu_init()
777 dev_err(gpu->dev, in etnaviv_gpu_init()
783 spin_lock_init(&gpu->event_spinlock); in etnaviv_gpu_init()
784 init_completion(&gpu->event_free); in etnaviv_gpu_init()
785 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); in etnaviv_gpu_init()
786 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) in etnaviv_gpu_init()
787 complete(&gpu->event_free); in etnaviv_gpu_init()
790 mutex_lock(&gpu->lock); in etnaviv_gpu_init()
791 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_init()
792 gpu->exec_state = -1; in etnaviv_gpu_init()
793 mutex_unlock(&gpu->lock); in etnaviv_gpu_init()
795 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_init()
796 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_init()
801 etnaviv_cmdbuf_free(&gpu->buffer); in etnaviv_gpu_init()
802 gpu->buffer.suballoc = NULL; in etnaviv_gpu_init()
804 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc); in etnaviv_gpu_init()
805 gpu->cmdbuf_suballoc = NULL; in etnaviv_gpu_init()
807 etnaviv_iommu_destroy(gpu->mmu); in etnaviv_gpu_init()
808 gpu->mmu = NULL; in etnaviv_gpu_init()
810 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_init()
812 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_init()
823 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) in verify_dma() argument
827 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
828 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
831 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
832 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
842 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_gpu_debugfs() argument
848 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); in etnaviv_gpu_debugfs()
850 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_debugfs()
854 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); in etnaviv_gpu_debugfs()
855 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); in etnaviv_gpu_debugfs()
856 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); in etnaviv_gpu_debugfs()
857 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_debugfs()
859 verify_dma(gpu, &debug); in etnaviv_gpu_debugfs()
863 gpu->identity.features); in etnaviv_gpu_debugfs()
865 gpu->identity.minor_features0); in etnaviv_gpu_debugfs()
867 gpu->identity.minor_features1); in etnaviv_gpu_debugfs()
869 gpu->identity.minor_features2); in etnaviv_gpu_debugfs()
871 gpu->identity.minor_features3); in etnaviv_gpu_debugfs()
873 gpu->identity.minor_features4); in etnaviv_gpu_debugfs()
875 gpu->identity.minor_features5); in etnaviv_gpu_debugfs()
877 gpu->identity.minor_features6); in etnaviv_gpu_debugfs()
879 gpu->identity.minor_features7); in etnaviv_gpu_debugfs()
881 gpu->identity.minor_features8); in etnaviv_gpu_debugfs()
883 gpu->identity.minor_features9); in etnaviv_gpu_debugfs()
885 gpu->identity.minor_features10); in etnaviv_gpu_debugfs()
887 gpu->identity.minor_features11); in etnaviv_gpu_debugfs()
891 gpu->identity.stream_count); in etnaviv_gpu_debugfs()
893 gpu->identity.register_max); in etnaviv_gpu_debugfs()
895 gpu->identity.thread_count); in etnaviv_gpu_debugfs()
897 gpu->identity.vertex_cache_size); in etnaviv_gpu_debugfs()
899 gpu->identity.shader_core_count); in etnaviv_gpu_debugfs()
901 gpu->identity.pixel_pipes); in etnaviv_gpu_debugfs()
903 gpu->identity.vertex_output_buffer_size); in etnaviv_gpu_debugfs()
905 gpu->identity.buffer_size); in etnaviv_gpu_debugfs()
907 gpu->identity.instruction_count); in etnaviv_gpu_debugfs()
909 gpu->identity.num_constants); in etnaviv_gpu_debugfs()
911 gpu->identity.varyings_count); in etnaviv_gpu_debugfs()
915 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; in etnaviv_gpu_debugfs()
943 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { in etnaviv_gpu_debugfs()
944 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); in etnaviv_gpu_debugfs()
945 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); in etnaviv_gpu_debugfs()
946 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); in etnaviv_gpu_debugfs()
974 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_debugfs()
976 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_debugfs()
982 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu) in etnaviv_gpu_recover_hang() argument
987 dev_err(gpu->dev, "recover hung GPU!\n"); in etnaviv_gpu_recover_hang()
989 if (pm_runtime_get_sync(gpu->dev) < 0) in etnaviv_gpu_recover_hang()
992 mutex_lock(&gpu->lock); in etnaviv_gpu_recover_hang()
994 etnaviv_hw_reset(gpu); in etnaviv_gpu_recover_hang()
996 /* complete all events, the GPU won't do it after the reset */ in etnaviv_gpu_recover_hang()
997 spin_lock_irqsave(&gpu->event_spinlock, flags); in etnaviv_gpu_recover_hang()
998 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) in etnaviv_gpu_recover_hang()
999 complete(&gpu->event_free); in etnaviv_gpu_recover_hang()
1000 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); in etnaviv_gpu_recover_hang()
1001 spin_unlock_irqrestore(&gpu->event_spinlock, flags); in etnaviv_gpu_recover_hang()
1002 gpu->completed_fence = gpu->active_fence; in etnaviv_gpu_recover_hang()
1004 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_recover_hang()
1005 gpu->lastctx = NULL; in etnaviv_gpu_recover_hang()
1006 gpu->exec_state = -1; in etnaviv_gpu_recover_hang()
1008 mutex_unlock(&gpu->lock); in etnaviv_gpu_recover_hang()
1009 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_recover_hang()
1011 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_recover_hang()
1016 struct etnaviv_gpu *gpu; member
1034 return dev_name(f->gpu->dev); in etnaviv_fence_get_timeline_name()
1041 return fence_completed(f->gpu, f->base.seqno); in etnaviv_fence_signaled()
1058 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) in etnaviv_gpu_fence_alloc() argument
1063 * GPU lock must already be held, otherwise fence completion order might in etnaviv_gpu_fence_alloc()
1066 lockdep_assert_held(&gpu->lock); in etnaviv_gpu_fence_alloc()
1072 f->gpu = gpu; in etnaviv_gpu_fence_alloc()
1074 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, in etnaviv_gpu_fence_alloc()
1075 gpu->fence_context, ++gpu->next_fence); in etnaviv_gpu_fence_alloc()
1084 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, in event_alloc() argument
1093 ret = wait_for_completion_timeout(&gpu->event_free, timeout); in event_alloc()
1096 dev_err(gpu->dev, "wait_for_completion_timeout failed"); in event_alloc()
1104 spin_lock_irqsave(&gpu->event_spinlock, flags); in event_alloc()
1107 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); in event_alloc()
1110 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); in event_alloc()
1111 set_bit(event, gpu->event_bitmap); in event_alloc()
1114 spin_unlock_irqrestore(&gpu->event_spinlock, flags); in event_alloc()
1120 complete(&gpu->event_free); in event_alloc()
1125 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) in event_free() argument
1129 spin_lock_irqsave(&gpu->event_spinlock, flags); in event_free()
1131 if (!test_bit(event, gpu->event_bitmap)) { in event_free()
1132 dev_warn(gpu->dev, "event %u is already marked as free", in event_free()
1134 spin_unlock_irqrestore(&gpu->event_spinlock, flags); in event_free()
1136 clear_bit(event, gpu->event_bitmap); in event_free()
1137 spin_unlock_irqrestore(&gpu->event_spinlock, flags); in event_free()
1139 complete(&gpu->event_free); in event_free()
1146 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, in etnaviv_gpu_wait_fence_interruptible() argument
1158 fence = idr_find(&gpu->fence_idr, id); in etnaviv_gpu_wait_fence_interruptible()
1190 * Although the retirement happens under the gpu lock, we don't want to hold
1193 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, in etnaviv_gpu_wait_obj_inactive() argument
1204 ret = wait_event_interruptible_timeout(gpu->fence_event, in etnaviv_gpu_wait_obj_inactive()
1215 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample() argument
1225 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); in sync_point_perfmon_sample()
1229 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample_pre() argument
1235 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_pre()
1237 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); in sync_point_perfmon_sample_pre()
1240 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_pre()
1242 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_pre()
1244 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); in sync_point_perfmon_sample_pre()
1247 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample_post() argument
1254 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); in sync_point_perfmon_sample_post()
1263 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_post()
1265 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_post()
1268 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_post()
1270 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); in sync_point_perfmon_sample_post()
1274 /* add bo's to gpu's ring, and kick gpu: */
1277 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_submit() local
1283 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_submit()
1285 pm_runtime_put_noidle(gpu->dev); in etnaviv_gpu_submit()
1293 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE in etnaviv_gpu_submit()
1295 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests in etnaviv_gpu_submit()
1301 ret = event_alloc(gpu, nr_events, event); in etnaviv_gpu_submit()
1304 pm_runtime_put_noidle(gpu->dev); in etnaviv_gpu_submit()
1308 mutex_lock(&gpu->lock); in etnaviv_gpu_submit()
1310 gpu_fence = etnaviv_gpu_fence_alloc(gpu); in etnaviv_gpu_submit()
1313 event_free(gpu, event[i]); in etnaviv_gpu_submit()
1318 gpu->active_fence = gpu_fence->seqno; in etnaviv_gpu_submit()
1321 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; in etnaviv_gpu_submit()
1323 gpu->event[event[1]].submit = submit; in etnaviv_gpu_submit()
1324 etnaviv_sync_point_queue(gpu, event[1]); in etnaviv_gpu_submit()
1327 gpu->event[event[0]].fence = gpu_fence; in etnaviv_gpu_submit()
1329 etnaviv_buffer_queue(gpu, submit->exec_state, event[0], in etnaviv_gpu_submit()
1333 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; in etnaviv_gpu_submit()
1335 gpu->event[event[2]].submit = submit; in etnaviv_gpu_submit()
1336 etnaviv_sync_point_queue(gpu, event[2]); in etnaviv_gpu_submit()
1340 mutex_unlock(&gpu->lock); in etnaviv_gpu_submit()
1347 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, in sync_point_worker() local
1349 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; in sync_point_worker()
1350 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in sync_point_worker()
1352 event->sync_point(gpu, event); in sync_point_worker()
1354 event_free(gpu, gpu->sync_point_event); in sync_point_worker()
1356 /* restart FE last to avoid GPU and IRQ racing against this worker */ in sync_point_worker()
1357 etnaviv_gpu_start_fe(gpu, addr + 2, 2); in sync_point_worker()
1360 static void dump_mmu_fault(struct etnaviv_gpu *gpu) in dump_mmu_fault() argument
1365 if (gpu->sec_mode == ETNA_SEC_NONE) in dump_mmu_fault()
1370 status = gpu_read(gpu, status_reg); in dump_mmu_fault()
1371 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); in dump_mmu_fault()
1379 if (gpu->sec_mode == ETNA_SEC_NONE) in dump_mmu_fault()
1384 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i, in dump_mmu_fault()
1385 gpu_read(gpu, address_reg)); in dump_mmu_fault()
1391 struct etnaviv_gpu *gpu = data; in irq_handler() local
1394 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); in irq_handler()
1399 pm_runtime_mark_last_busy(gpu->dev); in irq_handler()
1401 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); in irq_handler()
1404 dev_err(gpu->dev, "AXI bus error\n"); in irq_handler()
1409 dump_mmu_fault(gpu); in irq_handler()
1420 dev_dbg(gpu->dev, "event %u\n", event); in irq_handler()
1422 if (gpu->event[event].sync_point) { in irq_handler()
1423 gpu->sync_point_event = event; in irq_handler()
1424 queue_work(gpu->wq, &gpu->sync_point_work); in irq_handler()
1427 fence = gpu->event[event].fence; in irq_handler()
1431 gpu->event[event].fence = NULL; in irq_handler()
1442 if (fence_after(fence->seqno, gpu->completed_fence)) in irq_handler()
1443 gpu->completed_fence = fence->seqno; in irq_handler()
1446 event_free(gpu, event); in irq_handler()
1455 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) in etnaviv_gpu_clk_enable() argument
1459 if (gpu->clk_reg) { in etnaviv_gpu_clk_enable()
1460 ret = clk_prepare_enable(gpu->clk_reg); in etnaviv_gpu_clk_enable()
1465 if (gpu->clk_bus) { in etnaviv_gpu_clk_enable()
1466 ret = clk_prepare_enable(gpu->clk_bus); in etnaviv_gpu_clk_enable()
1471 if (gpu->clk_core) { in etnaviv_gpu_clk_enable()
1472 ret = clk_prepare_enable(gpu->clk_core); in etnaviv_gpu_clk_enable()
1477 if (gpu->clk_shader) { in etnaviv_gpu_clk_enable()
1478 ret = clk_prepare_enable(gpu->clk_shader); in etnaviv_gpu_clk_enable()
1486 if (gpu->clk_core) in etnaviv_gpu_clk_enable()
1487 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_enable()
1489 if (gpu->clk_bus) in etnaviv_gpu_clk_enable()
1490 clk_disable_unprepare(gpu->clk_bus); in etnaviv_gpu_clk_enable()
1492 if (gpu->clk_reg) in etnaviv_gpu_clk_enable()
1493 clk_disable_unprepare(gpu->clk_reg); in etnaviv_gpu_clk_enable()
1498 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) in etnaviv_gpu_clk_disable() argument
1500 if (gpu->clk_shader) in etnaviv_gpu_clk_disable()
1501 clk_disable_unprepare(gpu->clk_shader); in etnaviv_gpu_clk_disable()
1502 if (gpu->clk_core) in etnaviv_gpu_clk_disable()
1503 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_disable()
1504 if (gpu->clk_bus) in etnaviv_gpu_clk_disable()
1505 clk_disable_unprepare(gpu->clk_bus); in etnaviv_gpu_clk_disable()
1506 if (gpu->clk_reg) in etnaviv_gpu_clk_disable()
1507 clk_disable_unprepare(gpu->clk_reg); in etnaviv_gpu_clk_disable()
1512 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) in etnaviv_gpu_wait_idle() argument
1517 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_wait_idle()
1519 if ((idle & gpu->idle_mask) == gpu->idle_mask) in etnaviv_gpu_wait_idle()
1523 dev_warn(gpu->dev, in etnaviv_gpu_wait_idle()
1533 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_suspend() argument
1535 if (gpu->buffer.suballoc) { in etnaviv_gpu_hw_suspend()
1537 mutex_lock(&gpu->lock); in etnaviv_gpu_hw_suspend()
1538 etnaviv_buffer_end(gpu); in etnaviv_gpu_hw_suspend()
1539 mutex_unlock(&gpu->lock); in etnaviv_gpu_hw_suspend()
1546 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_gpu_hw_suspend()
1549 return etnaviv_gpu_clk_disable(gpu); in etnaviv_gpu_hw_suspend()
1553 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_resume() argument
1557 ret = mutex_lock_killable(&gpu->lock); in etnaviv_gpu_hw_resume()
1561 etnaviv_gpu_update_clock(gpu); in etnaviv_gpu_hw_resume()
1562 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_hw_resume()
1564 gpu->lastctx = NULL; in etnaviv_gpu_hw_resume()
1565 gpu->exec_state = -1; in etnaviv_gpu_hw_resume()
1567 mutex_unlock(&gpu->lock); in etnaviv_gpu_hw_resume()
1586 struct etnaviv_gpu *gpu = cdev->devdata; in etnaviv_gpu_cooling_get_cur_state() local
1588 *state = gpu->freq_scale; in etnaviv_gpu_cooling_get_cur_state()
1597 struct etnaviv_gpu *gpu = cdev->devdata; in etnaviv_gpu_cooling_set_cur_state() local
1599 mutex_lock(&gpu->lock); in etnaviv_gpu_cooling_set_cur_state()
1600 gpu->freq_scale = state; in etnaviv_gpu_cooling_set_cur_state()
1601 if (!pm_runtime_suspended(gpu->dev)) in etnaviv_gpu_cooling_set_cur_state()
1602 etnaviv_gpu_update_clock(gpu); in etnaviv_gpu_cooling_set_cur_state()
1603 mutex_unlock(&gpu->lock); in etnaviv_gpu_cooling_set_cur_state()
1619 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_bind() local
1623 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, in etnaviv_gpu_bind()
1624 (char *)dev_name(dev), gpu, &cooling_ops); in etnaviv_gpu_bind()
1625 if (IS_ERR(gpu->cooling)) in etnaviv_gpu_bind()
1626 return PTR_ERR(gpu->cooling); in etnaviv_gpu_bind()
1629 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); in etnaviv_gpu_bind()
1630 if (!gpu->wq) { in etnaviv_gpu_bind()
1635 ret = etnaviv_sched_init(gpu); in etnaviv_gpu_bind()
1640 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_bind()
1642 ret = etnaviv_gpu_clk_enable(gpu); in etnaviv_gpu_bind()
1648 gpu->drm = drm; in etnaviv_gpu_bind()
1649 gpu->fence_context = dma_fence_context_alloc(1); in etnaviv_gpu_bind()
1650 idr_init(&gpu->fence_idr); in etnaviv_gpu_bind()
1651 spin_lock_init(&gpu->fence_spinlock); in etnaviv_gpu_bind()
1653 INIT_WORK(&gpu->sync_point_work, sync_point_worker); in etnaviv_gpu_bind()
1654 init_waitqueue_head(&gpu->fence_event); in etnaviv_gpu_bind()
1656 priv->gpu[priv->num_gpus++] = gpu; in etnaviv_gpu_bind()
1658 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_bind()
1659 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_bind()
1664 etnaviv_sched_fini(gpu); in etnaviv_gpu_bind()
1667 destroy_workqueue(gpu->wq); in etnaviv_gpu_bind()
1671 thermal_cooling_device_unregister(gpu->cooling); in etnaviv_gpu_bind()
1679 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_unbind() local
1681 DBG("%s", dev_name(gpu->dev)); in etnaviv_gpu_unbind()
1683 flush_workqueue(gpu->wq); in etnaviv_gpu_unbind()
1684 destroy_workqueue(gpu->wq); in etnaviv_gpu_unbind()
1686 etnaviv_sched_fini(gpu); in etnaviv_gpu_unbind()
1689 pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_unbind()
1690 pm_runtime_put_sync_suspend(gpu->dev); in etnaviv_gpu_unbind()
1692 etnaviv_gpu_hw_suspend(gpu); in etnaviv_gpu_unbind()
1695 if (gpu->buffer.suballoc) in etnaviv_gpu_unbind()
1696 etnaviv_cmdbuf_free(&gpu->buffer); in etnaviv_gpu_unbind()
1698 if (gpu->cmdbuf_suballoc) { in etnaviv_gpu_unbind()
1699 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc); in etnaviv_gpu_unbind()
1700 gpu->cmdbuf_suballoc = NULL; in etnaviv_gpu_unbind()
1703 if (gpu->mmu) { in etnaviv_gpu_unbind()
1704 etnaviv_iommu_destroy(gpu->mmu); in etnaviv_gpu_unbind()
1705 gpu->mmu = NULL; in etnaviv_gpu_unbind()
1708 gpu->drm = NULL; in etnaviv_gpu_unbind()
1709 idr_destroy(&gpu->fence_idr); in etnaviv_gpu_unbind()
1712 thermal_cooling_device_unregister(gpu->cooling); in etnaviv_gpu_unbind()
1713 gpu->cooling = NULL; in etnaviv_gpu_unbind()
1732 struct etnaviv_gpu *gpu; in etnaviv_gpu_platform_probe() local
1736 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); in etnaviv_gpu_platform_probe()
1737 if (!gpu) in etnaviv_gpu_platform_probe()
1740 gpu->dev = &pdev->dev; in etnaviv_gpu_platform_probe()
1741 mutex_init(&gpu->lock); in etnaviv_gpu_platform_probe()
1742 mutex_init(&gpu->fence_lock); in etnaviv_gpu_platform_probe()
1746 gpu->mmio = devm_ioremap_resource(&pdev->dev, res); in etnaviv_gpu_platform_probe()
1747 if (IS_ERR(gpu->mmio)) in etnaviv_gpu_platform_probe()
1748 return PTR_ERR(gpu->mmio); in etnaviv_gpu_platform_probe()
1751 gpu->irq = platform_get_irq(pdev, 0); in etnaviv_gpu_platform_probe()
1752 if (gpu->irq < 0) { in etnaviv_gpu_platform_probe()
1753 dev_err(dev, "failed to get irq: %d\n", gpu->irq); in etnaviv_gpu_platform_probe()
1754 return gpu->irq; in etnaviv_gpu_platform_probe()
1757 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, in etnaviv_gpu_platform_probe()
1758 dev_name(gpu->dev), gpu); in etnaviv_gpu_platform_probe()
1760 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); in etnaviv_gpu_platform_probe()
1765 gpu->clk_reg = devm_clk_get(&pdev->dev, "reg"); in etnaviv_gpu_platform_probe()
1766 DBG("clk_reg: %p", gpu->clk_reg); in etnaviv_gpu_platform_probe()
1767 if (IS_ERR(gpu->clk_reg)) in etnaviv_gpu_platform_probe()
1768 gpu->clk_reg = NULL; in etnaviv_gpu_platform_probe()
1770 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus"); in etnaviv_gpu_platform_probe()
1771 DBG("clk_bus: %p", gpu->clk_bus); in etnaviv_gpu_platform_probe()
1772 if (IS_ERR(gpu->clk_bus)) in etnaviv_gpu_platform_probe()
1773 gpu->clk_bus = NULL; in etnaviv_gpu_platform_probe()
1775 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); in etnaviv_gpu_platform_probe()
1776 DBG("clk_core: %p", gpu->clk_core); in etnaviv_gpu_platform_probe()
1777 if (IS_ERR(gpu->clk_core)) in etnaviv_gpu_platform_probe()
1778 gpu->clk_core = NULL; in etnaviv_gpu_platform_probe()
1779 gpu->base_rate_core = clk_get_rate(gpu->clk_core); in etnaviv_gpu_platform_probe()
1781 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader"); in etnaviv_gpu_platform_probe()
1782 DBG("clk_shader: %p", gpu->clk_shader); in etnaviv_gpu_platform_probe()
1783 if (IS_ERR(gpu->clk_shader)) in etnaviv_gpu_platform_probe()
1784 gpu->clk_shader = NULL; in etnaviv_gpu_platform_probe()
1785 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); in etnaviv_gpu_platform_probe()
1788 dev_set_drvdata(dev, gpu); in etnaviv_gpu_platform_probe()
1795 pm_runtime_use_autosuspend(gpu->dev); in etnaviv_gpu_platform_probe()
1796 pm_runtime_set_autosuspend_delay(gpu->dev, 200); in etnaviv_gpu_platform_probe()
1797 pm_runtime_enable(gpu->dev); in etnaviv_gpu_platform_probe()
1818 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_rpm_suspend() local
1822 if (gpu->completed_fence != gpu->active_fence) in etnaviv_gpu_rpm_suspend()
1826 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; in etnaviv_gpu_rpm_suspend()
1827 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; in etnaviv_gpu_rpm_suspend()
1831 return etnaviv_gpu_hw_suspend(gpu); in etnaviv_gpu_rpm_suspend()
1836 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_rpm_resume() local
1839 ret = etnaviv_gpu_clk_enable(gpu); in etnaviv_gpu_rpm_resume()
1844 if (gpu->drm && gpu->buffer.suballoc) { in etnaviv_gpu_rpm_resume()
1845 ret = etnaviv_gpu_hw_resume(gpu); in etnaviv_gpu_rpm_resume()
1847 etnaviv_gpu_clk_disable(gpu); in etnaviv_gpu_rpm_resume()
1863 .name = "etnaviv-gpu",