Lines Matching full:output

27 /* Y 1st frame start address for output DMA */
29 /* Y 2nd frame start address for output DMA */
31 /* Y 3rd frame start address for output DMA */
33 /* Y 4th frame start address for output DMA */
35 /* Cb 1st frame start address for output DMA */
37 /* Cb 2nd frame start address for output DMA */
39 /* Cb 3rd frame start address for output DMA */
41 /* Cb 4th frame start address for output DMA */
43 /* Cr 1st frame start address for output DMA */
45 /* Cr 2nd frame start address for output DMA */
47 /* Cr 3rd frame start address for output DMA */
49 /* Cr 4th frame start address for output DMA */
53 /* Output DMA control */
95 /* Output DMA Y offset */
97 /* Output DMA CB offset */
99 /* Output DMA CR offset */
109 /* Output DMA original image size */
111 /* Real output DMA image size */
121 /* Output Frame Buffer Sequence */
123 /* Y 5th frame start address for output DMA */
125 /* Y 6th frame start address for output DMA */
127 /* Y 7th frame start address for output DMA */
129 /* Y 8th frame start address for output DMA */
131 /* Y 9th frame start address for output DMA */
133 /* Y 10th frame start address for output DMA */
135 /* Y 11th frame start address for output DMA */
137 /* Y 12th frame start address for output DMA */
139 /* Y 13th frame start address for output DMA */
141 /* Y 14th frame start address for output DMA */
143 /* Y 15th frame start address for output DMA */
145 /* Y 16th frame start address for output DMA */
147 /* Y 17th frame start address for output DMA */
149 /* Y 18th frame start address for output DMA */
151 /* Y 19th frame start address for output DMA */
153 /* Y 20th frame start address for output DMA */
155 /* Y 21th frame start address for output DMA */
157 /* Y 22th frame start address for output DMA */
159 /* Y 23th frame start address for output DMA */
161 /* Y 24th frame start address for output DMA */
163 /* Y 25th frame start address for output DMA */
165 /* Y 26th frame start address for output DMA */
167 /* Y 27th frame start address for output DMA */
169 /* Y 28th frame start address for output DMA */
171 /* Y 29th frame start address for output DMA */
173 /* Y 30th frame start address for output DMA */
175 /* Y 31th frame start address for output DMA */
177 /* Y 32th frame start address for output DMA */
180 /* CB 5th frame start address for output DMA */
182 /* CB 6th frame start address for output DMA */
184 /* CB 7th frame start address for output DMA */
186 /* CB 8th frame start address for output DMA */
188 /* CB 9th frame start address for output DMA */
190 /* CB 10th frame start address for output DMA */
192 /* CB 11th frame start address for output DMA */
194 /* CB 12th frame start address for output DMA */
196 /* CB 13th frame start address for output DMA */
198 /* CB 14th frame start address for output DMA */
200 /* CB 15th frame start address for output DMA */
202 /* CB 16th frame start address for output DMA */
204 /* CB 17th frame start address for output DMA */
206 /* CB 18th frame start address for output DMA */
208 /* CB 19th frame start address for output DMA */
210 /* CB 20th frame start address for output DMA */
212 /* CB 21th frame start address for output DMA */
214 /* CB 22th frame start address for output DMA */
216 /* CB 23th frame start address for output DMA */
218 /* CB 24th frame start address for output DMA */
220 /* CB 25th frame start address for output DMA */
222 /* CB 26th frame start address for output DMA */
224 /* CB 27th frame start address for output DMA */
226 /* CB 28th frame start address for output DMA */
228 /* CB 29th frame start address for output DMA */
230 /* CB 30th frame start address for output DMA */
232 /* CB 31th frame start address for output DMA */
234 /* CB 32th frame start address for output DMA */
237 /* CR 5th frame start address for output DMA */
239 /* CR 6th frame start address for output DMA */
241 /* CR 7th frame start address for output DMA */
243 /* CR 8th frame start address for output DMA */
245 /* CR 9th frame start address for output DMA */
247 /* CR 10th frame start address for output DMA */
249 /* CR 11th frame start address for output DMA */
251 /* CR 12th frame start address for output DMA */
253 /* CR 13th frame start address for output DMA */
255 /* CR 14th frame start address for output DMA */
257 /* CR 15th frame start address for output DMA */
259 /* CR 16th frame start address for output DMA */
261 /* CR 17th frame start address for output DMA */
263 /* CR 18th frame start address for output DMA */
265 /* CR 19th frame start address for output DMA */
267 /* CR 20th frame start address for output DMA */
269 /* CR 21th frame start address for output DMA */
271 /* CR 22th frame start address for output DMA */
273 /* CR 23th frame start address for output DMA */
275 /* CR 24th frame start address for output DMA */
277 /* CR 25th frame start address for output DMA */
279 /* CR 26th frame start address for output DMA */
281 /* CR 27th frame start address for output DMA */
283 /* CR 28th frame start address for output DMA */
285 /* CR 29th frame start address for output DMA */
287 /* CR 30th frame start address for output DMA */
289 /* CR 31th frame start address for output DMA */
291 /* CR 32th frame start address for output DMA */
488 /* Output DMA control register */